SCM Application in Semiconductor Failure Analysis and Possible Solution for Well Inspection of Advanced Nanometer Process

Author(s):  
Coswin Lin ◽  
Chia-Hsing Chao

Abstract Scanning capacitance microscopy (SCM) is a powerful technique that may readily be applied to semiconductor failure analysis yielding information on problems stemming from doping issues. This paper details the study of a current leakage failure and outlines the use of the SCM technique for shallow trench isolation applications. A two-step sample preparation technique involving firstly, Chemical Mechanical Polishing (CMP) followed by a wet etch, could improve the sample surface planarization allowing SCM inspection of the STI region.

Author(s):  
Pradip Sairam Pichumani ◽  
Fauzia Khatkhatay

Abstract Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.


Author(s):  
C.S. Bonifacio ◽  
P. Nowakowski ◽  
R. Li ◽  
M.L. Ray ◽  
P.E. Fischione ◽  
...  

Abstract Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.


2004 ◽  
Vol 816 ◽  
Author(s):  
David R. Evans

AbstractThe use of cerium oxide (ceria) as an abrasive for dielectric chemical mechanical polishing has a “checkered” history to say the least. Nevertheless, its use remains attractive for this purpose because of favorable polishing characteristics that are generally not obtainable using conventional fumed or colloidal silica abrasives. To be specific, large differences are commonly observed between removal rates of thin film silicon oxide, silicon nitride, and/or polysilicon. Moreover, such rate selectivity invariably favors removal of oxide films, which of course, is precisely what is desirable for fabrication of modern shallow trench isolation schemes. Even so, CMP using ceria abrasive often exhibits unusual characteristics that cannot be explained adequately by conventional polishing models based on pad/asperity elasticity or pressure distribution over features. Most notably, non-conventional, observed behaviors can be collected under the rubric of “slow start phenomena”. In this work, it is asserted that specific polishing characteristics of ceria slurry are largely due to the detailed surface chemistry of ceria particles and their interaction with silica. In any case, it is further shown that modification of slurry lubrication can alleviate slow-start and shift CMP process characteristics back toward more conventional behavior.


Sign in / Sign up

Export Citation Format

Share Document