A gate-oxide-breakdown antifuse OTP ROM array based on TSMC 90nm process

2008 ◽

Author(s):

K.A. Mohammad ◽

L.J. Liu ◽

S.F. Liew ◽

S.F. Chong ◽

D.G. Lee ◽

...

Keyword(s):

Failure Analysis ◽

Gate Oxide ◽

Action Plans ◽

Preventive Action ◽

Oxide Breakdown ◽

Reliability Level ◽

The Future ◽

Dry Etch ◽

Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Download Full-text

Fundamental Considerations for CDM Failure in 90nm Products

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0055 ◽

2006 ◽

Author(s):

Nobuyuki Wakai ◽

Yuji Kobira ◽

Hidemitsu Egawa ◽

Masayoshi Tsutsumi

Keyword(s):

Breakdown Voltage ◽

High Speed ◽

Gate Oxide ◽

Critical Parameters ◽

Protection Device ◽

Oxide Breakdown ◽

Technology Products ◽

Charged Device ◽

Device Size ◽

Fundamental Consideration

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

Download Full-text

LDMOST gate oxide breakdown prediction under realistic RF power application conditions

2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) ◽

10.1109/ipfa.2017.8060122 ◽

2017 ◽

Cited By ~ 2

Author(s):

Guoqiao Tao ◽

Sjoerd van Nederveen ◽

Mario de Vaan

Keyword(s):

Gate Oxide ◽

Rf Power ◽

Oxide Breakdown ◽

Power Application

Download Full-text

Effect of gate oxide breakdown on RF device and circuit performance

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual. ◽

10.1109/relphy.2003.1197711 ◽

2003 ◽

Cited By ~ 18

Author(s):

Hong Yang ◽

J.S. Yuan ◽

Enjun Xiao

Keyword(s):

Gate Oxide ◽

Circuit Performance ◽

Oxide Breakdown

Download Full-text

Explanation of nMOSFET substrate current after hard gate oxide breakdown

Microelectronic Engineering ◽

10.1016/s0167-9317(01)00659-1 ◽

2001 ◽

Vol 59 (1-4) ◽

pp. 155-160 ◽

Cited By ~ 5

Author(s):

B Kaczer ◽

R Degraeve ◽

A De Keersgieter ◽

M Rasras ◽

G Groeseneken

Keyword(s):

Gate Oxide ◽

Oxide Breakdown ◽

Substrate Current

Download Full-text

Dependence of Reliability of Ultrathin Mos Gate Oxides on the Fermi Level Positions at Gate and Substrate

MRS Proceedings ◽

10.1557/proc-473-123 ◽

1997 ◽

Vol 473 ◽

Cited By ~ 1

Author(s):

Tien-Chun Yang ◽

Navakanta Bhat ◽

Krishna C. Saraswat

Keyword(s):

Electric Field ◽

Fermi Level ◽

Breakdown Strength ◽

Gate Oxide ◽

High Energy ◽

Constant Current ◽

Oxide Breakdown ◽

Mos Devices ◽

High Energy Electrons ◽

Substrate Doping

ABSTRACTWe demonstrate that the reliability of ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on the position at the substrate for constant current gate injection (Vg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of oxides is closely related to the electric field across the gate oxide, which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field must be higher to give the same injection current density. A higher electric field gives more high energy electrons at the anode, and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field, and as a result, they do not influence the degradation.

Download Full-text

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/hiten-ta13 ◽

2013 ◽

Vol 2013 (HITEN) ◽

pp. 000116-000121

Author(s):

K. Grella ◽

S. Dreiner ◽

H. Vogt ◽

U. Paschen

Keyword(s):

High Temperature ◽

Dielectric Breakdown ◽

Gate Oxide ◽

Oxide Thickness ◽

Cmos Technology ◽

Silicon On Insulator ◽

Cmos Process ◽

Oxide Breakdown ◽

Time Dependent Dielectric Breakdown ◽

Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Download Full-text