Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2020 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

scholarly journals SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2021 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

scholarly journals SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2021 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Device Ioff Mapping—Analysis of Ring Oscillator by Optical Beam Induced Resistance Change

2015 ◽  
Author(s):  
Greg M. Johnson ◽  
Ziyan Xu ◽  
Christopher D’Aleo
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Ring Oscillator ◽  
Ring Oscillators ◽  
Rapid Improvement ◽  
Resistance Change ◽  
Emission Analysis ◽  
Multiple Defect ◽  
Line Technology

Abstract The ring oscillator is an important tool for inline monitoring during technology development, as it contains the most important front end of line technology features, is testable at first metal, and generally shows a good correlation to SRAM yield. This work explores various failure analysis techniques for the ring oscillator, during the development of 14 nm FinFET technology. OBIRCH, which is typically a DC technique, was operated with voltages as low as 0.15 V to find multiple defect mechanisms affecting the yield of ring oscillators, which operate at a frequencies in the GHz range. In contrast to typical photon emission analysis of ring oscillators, examines the devices which are flipping on, it is here proposed that the OBIRCH spots which are generated are indications of the Ioff, or the leakage of devices in the inverter stages across the ring. The results from this failure analysis approach enabled a rapid improvement in yield not only of the ring oscillator itself but of the SRAM.

MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing

2019 ◽  
Author(s):  
Jessica Yang ◽  
Omprakash Rengaraj ◽  
Puneet Gupta ◽  
Rudolf Schlangen
Keyword(s):  
Failure Analysis ◽  
Photon Emission ◽  
Random Access ◽  
Random Access Memory ◽  
Fault Isolation ◽  
Static Random Access Memory ◽  
Production Testing ◽  
Access Memory ◽  
Electrical Failure ◽  
Voltage Imaging

Abstract Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Overview of Wafer-level Electrical Failure Analysis Process for Accelerated Yield Engineering

2019 ◽  
pp. 1-9
Author(s):  
S.H. Goh ◽  
Y.H. Chan ◽  
B.L. Yeoh ◽  
H. Hao ◽  
M.H. Thor ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Process

Speed Path Analysis: A Connection Between Speed Degradation, Silicon Dislocations, and Light Induced Voltage Alteration

2003 ◽  
Author(s):  
D. Davis
Keyword(s):  
Failure Analysis ◽  
Path Analysis ◽  
Standard Test ◽  
Induced Voltage ◽  
Test Program ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Current Voltage

Abstract The failure analyst is often times challenged with the analysis of devices that fail due to speed degradation. These are units that pass the entire standard test program as long as the speed at which the device is tested is kept below a certain level. Many times, these units are binned and sold to customers at reduced prices. The unresolved rate for these types of failures is often sporadic and at times there isn’t any defect that is physically observable or detectable with global EFA (electrical failure analysis) techniques. These devices are usually from an advanced process where a shift in performance such as current, voltage, and speed (frequency) is common.

Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing

2011 ◽  
Author(s):  
Steven Kasapi ◽  
William Lo ◽  
Joy Liao ◽  
Bruce Cory ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Wafer Level ◽  
Root Cause ◽  
Non Invasive ◽  
Laser Probing ◽  
Volume Yield ◽  
Scan Chain ◽  
Leakage Failure ◽  
Root Cause Identification

Abstract A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.

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