Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing

2011 ◽  
Author(s):  
Steven Kasapi ◽  
William Lo ◽  
Joy Liao ◽  
Bruce Cory ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Wafer Level ◽  
Root Cause ◽  
Non Invasive ◽  
Laser Probing ◽  
Volume Yield ◽  
Scan Chain ◽  
Leakage Failure ◽  
Root Cause Identification

Abstract A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.

Root Cause Finding of a Diode Leakage Failure Using Scanning Magnetic Microscopy and ToF-SIMS as Key Methods

2006 ◽  
Author(s):  
H. Preu ◽  
W. Mack ◽  
T. Kilger ◽  
B. Seidl ◽  
J. Walter ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Quantum Interference ◽  
Leakage Currents ◽  
Root Cause ◽  
Microelectronic Devices ◽  
Successful Approach ◽  
Magnetic Microscopy ◽  
Leakage Failure ◽  
Root Cause Identification

Abstract One challenge in failure analysis of microelectronic devices is the localization and root cause finding of leakage currents in passives. In this case study we present a successful approach for failure analysis of a diode leakage failure. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToFSIMS as key methods for localization and root cause identification. [1]

Advancement in Data Engineering and Feature Processing Workflow by Using Deep Learning Techniques for the Automation of ESP Failure Root Cause Analyses

2021 ◽  
Author(s):  
Saniya Karnik ◽  
Navya Yenuganti ◽  
Bonang Firmansyah Jusri ◽  
Supriya Gupta ◽  
Prasanna Nirgudkar ◽  
...  
Keyword(s):  
Deep Learning ◽  
Failure Analysis ◽  
Language Processing ◽  
Turnaround Time ◽  
Process Efficiency ◽  
Root Cause ◽  
Feature Processing ◽  
Learning Techniques ◽  
Electrical Submersible Pump ◽  
Root Cause Identification

Abstract Today, Electrical Submersible Pump (ESP) failure analysis is a tedious, human-intensive, and time-consuming activity involving dismantle, inspection, and failure analysis (DIFA) for each failure. This paper presents a novel artificial intelligence workflow using an ensemble of machine learning (ML) algorithms coupled with natural language processing (NLP) and deep learning (DL). The algorithms outlined in this paper bring together structured and unstructured data across equipment, production, operations, and failure reports to automate root cause identification and analysis post breakdown. This process will result in reduced turnaround time (TAT) and human effort thus drastically improving process efficiency.

Symptom or Cause? A Case Study

2015 ◽  
Author(s):  
Anuradha Swaminathan ◽  
Joy Liao ◽  
Howard Marks
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Analysis Data ◽  
Continuous Wave Laser ◽  
Electrical Failure ◽  
Root Cause ◽  
First Case ◽  
Successful Analysis ◽  
28 Nm

Abstract Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.

An Effective and Practical Analysis Technique for Open Defect Isolation at IDD Leakage Failure by Observing Transient Photo Emission

1998 ◽  
Author(s):  
A. Nishikawa ◽  
N.I. Kato ◽  
J. Matsuzawa ◽  
K. Takagi ◽  
N. Miura
Keyword(s):  
Failure Analysis ◽  
Transient Behavior ◽  
Cross Sectional ◽  
Root Cause ◽  
Analysis Technique ◽  
Defect Isolation ◽  
Electron Image ◽  
Open Defects ◽  
Leakage Failure ◽  
Current Emission

Abstract A new analysis method using conventional emission microscopy (EMS) was developed for localizing open defects in CMOS LSIs. EMS is widely used for failure analysis of IDD (power supply current) leakage failures. The root cause of a failure is deduced by considering the emission characteristics associated with the IDD leakage current, emission shape, emission energy spectrum, and exact location on an Si die. Our new technique focuses on the observation of transient photoemission immediately after VDD application. During IDD leakage failure analysis, unique transient photoemission characteristics are observed. Immediately after VDD application, strong photoemission is briefly observed at the drain edge of an n-FET, but disappears after stabilization of the IDD current. We assumed that temporary photoemission would not be generated in transient behavior unless some kind of open defects were located at a specific conductor connected to the gate electrode. This mechanism was verified by nonbiased charge-up contrast of a conventional secondary electron image (SEI) and cross-sectional SEM observation at the defective open location. The dynamic method of observing transient photoemission proposed here is a very effective and practical way for detecting the locations of open failures in CMOS LSIs. Some examples of open mode failure analysis are described, along with cross-sectional TEM observations.

Failure Mechanism Studies and Root Cause Identification of Nonstick on Pad on Microchip Al Bondpads

2014 ◽  
Author(s):  
Hua Younan ◽  
Zhou Yongkai ◽  
Chen Yixin ◽  
Fu Chao ◽  
Li Xiaomin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Wafer Fabrication ◽  
Assembly Process ◽  
Root Cause ◽  
Barrier Metal ◽  
Root Cause Identification ◽  
Induced Defects

Abstract It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.

Scan-Shift Debug Using LVI Phase Mapping

2013 ◽  
Author(s):  
Yin (Roy) S. Ng ◽  
Howard Marks ◽  
Christopher Nemirov ◽  
Chun-Cheng Tsao ◽  
Jim Vickers
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Continuous Wave Laser ◽  
Success Rates ◽  
Established Method ◽  
Electrical Failure ◽  
Voltage Imaging ◽  
Integrity Tests ◽  
Scan Chain ◽  
Domain Information

Abstract Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Fast Root Cause Identification Using Combination of Failure Analysis and In-Line Inspection

2017 ◽  
Author(s):  
Zhigang Song ◽  
Weihao Weng ◽  
Brett Engel
Keyword(s):  
Failure Analysis ◽  
Process Development ◽  
Second Step ◽  
Line Defect ◽  
Semiconductor Technology ◽  
Process Step ◽  
Root Cause ◽  
The Past ◽  
Root Cause Identification ◽  
The Relationship

Abstract Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

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