Device Ioff Mapping—Analysis of Ring Oscillator by Optical Beam Induced Resistance Change

2015 ◽  
Author(s):  
Greg M. Johnson ◽  
Ziyan Xu ◽  
Christopher D’Aleo
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Ring Oscillator ◽  
Ring Oscillators ◽  
Rapid Improvement ◽  
Resistance Change ◽  
Emission Analysis ◽  
Multiple Defect ◽  
Line Technology

Abstract The ring oscillator is an important tool for inline monitoring during technology development, as it contains the most important front end of line technology features, is testable at first metal, and generally shows a good correlation to SRAM yield. This work explores various failure analysis techniques for the ring oscillator, during the development of 14 nm FinFET technology. OBIRCH, which is typically a DC technique, was operated with voltages as low as 0.15 V to find multiple defect mechanisms affecting the yield of ring oscillators, which operate at a frequencies in the GHz range. In contrast to typical photon emission analysis of ring oscillators, examines the devices which are flipping on, it is here proposed that the OBIRCH spots which are generated are indications of the Ioff, or the leakage of devices in the inverter stages across the ring. The results from this failure analysis approach enabled a rapid improvement in yield not only of the ring oscillator itself but of the SRAM.

Techniques to Remove the C4 Die from a Ceramic Package

1998 ◽  
Author(s):  
Mehrdad Mahanpour ◽  
Andy Gray ◽  
Jose Hulog ◽  
Pat Chang
Keyword(s):  
Failure Analysis ◽  
Photon Emission ◽  
Emission Analysis ◽  
Methods And Techniques

Abstract C4 (Controlled Collapse Chip Connection) failure analysis compared to conventional packages (DIP- LCC- QFP, etc.) is not trivial. For instance, one has to thin the C4 die for IR microscope inspection or for photon emission analysis. Then, after failure analysis on the die, it must be removed for deprocessing or further analysis. Three methods and techniques will be discussed for removing the C4 die from the package without damaging the die. However, for each technique it is very important to know the condition of the die and package prior to die removal. The method used will differ, for example, if the die is thinned or not.

Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission

2014 ◽  
Author(s):  
Thierry Parrassin ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
Hervé Deslandes
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Light Emission ◽  
Photon Emission ◽  
Optical Path ◽  
Spectral Mapping ◽  
Additional Information ◽  
Transmission Grating ◽  
Emission System ◽  
Advance Knowledge

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.

Application of Novel Low Current OBIRCH Amplifier and Nanoprobing to Identify Subtle Leakages in Advanced Node Technologies

2018 ◽  
Author(s):  
Satish Kodali ◽  
Liangshan Chen ◽  
Yuting Wei ◽  
Tanya Schaeffer ◽  
Chong Khiam Oh
Keyword(s):  
Signal To Noise Ratio ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Ring Oscillator ◽  
High Signal ◽  
The Novel ◽  
Resistance Change ◽  
Three Samples ◽  
Relative Threshold ◽  
First Time

Abstract Optical beam induced resistance change (OBIRCH) is a very well-adapted technique for static fault isolation in the semiconductor industry. Novel low current OBIRCH amplifier is used to facilitate safe test condition requirements for advanced nodes. This paper shows the differences between the earlier and novel generation OBIRCH amplifiers. Ring oscillator high standby leakage samples are analyzed using the novel generation amplifier. High signal to noise ratio at applied low bias and current levels on device under test are shown on various samples. Further, a metric to demonstrate the SNR to device performance is also discussed. OBIRCH analysis is performed on all the three samples for nanoprobing of, and physical characterization on, the leakage. The resulting spots were calibrated and classified. It is noted that the calibration metric can be successfully used for the first time to estimate the relative threshold voltage of individual transistors in advanced process nodes.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results

2003 ◽  
Author(s):  
Steve Ferrier ◽  
Kevin D. Martin ◽  
Donald Schulte
Keyword(s):  
Failure Analysis ◽  
Formal Analysis ◽  
Photon Emission ◽  
Flow Analysis ◽  
Formal Structure ◽  
Ic Design ◽  
Analysis Process ◽  
Secondary Failure ◽  
Leakage Failure ◽  
Wafer Manufacturing

Abstract Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2020 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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