Power Distribution Analysis of an Integrated Circuit Using FIB Passive Voltage Contrast

2016 ◽  
Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer
Keyword(s):  
Power Management ◽  
Integrated Circuit ◽  
Power Distribution ◽  
Metal Layer ◽  
Distribution Analysis ◽  
Sem Imaging ◽  
Voltage Contrast ◽  
Level Analysis ◽  
Graphic Database ◽  
Architecture Analysis

Abstract Competitive circuit analysis of an Integrated Circuit (IC) is one of the most challenging types of analysis. It involves various high technology steps of IC die de-processing/de-layering; keeping precise planarity from metal layer to metal layer, Scanning Electron Microscope (SEM) imaging and images mosaicking, image recognition and Graphic Database System (GDS) segmentation processes and finally logic and architecture level analysis. One of the most complicated analysis is Power Management and Power Distribution [2] on the entire IC die when no datasheet or other IC’s information is available. Power Distribution analysis requires the highest level of architecture analysis, not feasible by conventional Reverse Engineering (RE) methods or extremely costly. The current paper discusses and demonstrates a new inventive methodology of Power Distribution analysis using known FIB Passive Voltage Contrast (PVC) effects [1]. This patented technique provides significant time and resources saving.

Circuit Tracing on Integrated Circuit Using FIB Passive Voltage Contrast Effect

2015 ◽  
Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer ◽  
Michael W. Phaneuf
Keyword(s):  
Electron Microscope ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Database System ◽  
Conventional Procedure ◽  
Sem Imaging ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Graphic Database

Abstract Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

Investigation of High Frequency Failures on a 0.35μm CMOS IC

1999 ◽  
Author(s):  
Alan Kennen ◽  
John F. Guravage ◽  
Lauren Foster ◽  
John Kornblum
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Ion Beam ◽  
Stress Test ◽  
Design For Test ◽  
Interface Failure ◽  
Serial Interface ◽  
High Impedance

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

Proof of Reverse Engineering Barrier: SEM Image Analysis on Covert Gates

2021 ◽  
Author(s):  
Tasnuva Farheen ◽  
Ulbert Botero ◽  
Nitin Varshney ◽  
Damon L. Woodard ◽  
Mark Tehranipoor ◽  
...  
Keyword(s):  
Machine Learning ◽  
Reverse Engineering ◽  
Contact Structures ◽  
Imaging Analysis ◽  
Sem Image ◽  
Device Structures ◽  
Microscope Imaging ◽  
Sem Imaging ◽  
The Difference ◽  
Voltage Contrast

Abstract IC camouflaging has been proposed as a promising countermeasure against malicious reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as one single layout under microscope imaging, thereby hiding the real circuit functionality from adversaries. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits and thus being resilient against various invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis was only performed on simplified dummy contact structures in prior work. Whether the e-beam during SEM imaging will charge differently on different contacts and further reveal the different structures or not requires extended research. In this study, we fabricated real and dummy contacts in various structures and performed a systematic SEM imaging analysis to investigate the possible charging and the consequent passive voltage contrast on contacts. In addition, machine-learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant in SEM imaging, which effectively prevents adversarial SEM-based reverse engineering. Index Terms—Reverse Engineering, IC Camouflaging, Scanning Electron Microscopy, Machine Learning, Countermeasure.

Heterogeneous Integration for HPC and Data Centers

2019 ◽  
Vol 2019 (S2) ◽  
pp. S1-S26
Author(s):  
Kanad Ghose ◽  
Dale Becker
Keyword(s):  
Power Management ◽  
Power Distribution ◽  
Data Centers ◽  
System Level ◽  
Heterogeneous Integration

Abstract Invited Session on HETEROGENEOUS INTEGRATION ROADMAP - Heterogeneous Integration for HPC and Data Centers. This TWG focuses on the system-level implications related to performance, power management, security, power distribution issues and others

Power distribution, the environment, and public health: A state-level analysis

1999 ◽  
Vol 29 (1) ◽  
pp. 127-140 ◽  
Author(s):  
James K. Boyce ◽  
Andrew R. Klemer ◽  
Paul H. Templet ◽  
Cleve E. Willis
Keyword(s):  
Public Health ◽  
Power Distribution ◽  
State Level ◽  
Environment And Public Health ◽  
Level Analysis

A Power Management Integrated System for Biomass-based Marine Sediment Energy Harvesting

2014 ◽  
Vol 23 (01n02) ◽  
pp. 1450012 ◽  
Author(s):  
Guoxian Huang ◽  
Ridvan Umaz ◽  
Udayarka Karra ◽  
Baikun Li ◽  
Lei Wang
Keyword(s):  
Energy Harvesting ◽  
Power Management ◽  
Integrated Circuit ◽  
Electrical Energy ◽  
Energy Conversion Efficiency ◽  
Integrated System ◽  
Cmos Process ◽  
Energy Harvesting System ◽  
Metabolic Activities ◽  
Sustainable Power

This paper presents the design of an underwater energy harvesting system, which would provide persistent and sustainable power supply for remote underwater sensing and surveillance devices. The system consists of Distributed Benthic Microbial Fuel Cell (DBMFC) and the associated power management integrated circuit. The DBMFC exploits bacterial metabolic activities associated with the redox reaction to generate electrical energy directly from biodegradable substrates. The power management circuit collects the energy harvested by the DBMFC and boosts the output voltage to a sufficient and stable level for loads such as sensor devices. Simulation results of the power management system in a 90nm CMOS process demonstrate the expected functions and the significant improvement in energy conversion efficiency.

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