Case Study—Failure Analysis of a Printed Circuit Board Latent Failure and Resulting Implication of Weaknesses in Panel Coupons and Lot DPA

2017 ◽  
Author(s):  
Tom Tuite
Keyword(s):  
Failure Mechanism ◽  
Printed Circuit Board ◽  
Short Circuit ◽  
Circuit Board ◽  
System Level ◽  
Drilling Process ◽  
Printed Circuit ◽  
Root Cause ◽  
Ionic Contamination ◽  
Root Cause Identification

Abstract Multiple, independent, system level test failures that occurred around the same time were traced back to a short circuit on the same type of printed circuit board (PCB). The PCBs were removed from the application and sent to the authors' lab for analysis. This paper reviews the analysis techniques and results that led to the failure mechanism being identified. The discussion focuses on steps taken to exonerate the authors' lab and processes as possible sources of contamination. Additional investigation that leads to the conclusion that the issue is systemic is also covered. The paper then focuses on the containment effort as well as root cause identification at the manufacturers. It was concluded that the failure mechanism causing the short circuit in the failed PCB is due to ionic contamination trapped inside the PCB. The normal chemistry required to process the plated through holes contaminated the voids/fractures created by drilling process.

scholarly journals Root Cause Analysis of a Printed Circuit Board (PCB) Failure in a Public Transport Communication System

2022 ◽  
Vol 12 (2) ◽  
pp. 640
Author(s):  
Cher-Ming Tan ◽  
Hsiao-Hi Chen ◽  
Jing-Ping Wu ◽  
Vivek Sangwan ◽  
Kun-Yen Tsai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Essential Element ◽  
Circuit Board ◽  
Cause Analysis ◽  
Printed Circuit ◽  
Root Cause ◽  
Burn Out ◽  
Root Cause Identification

A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

Temperature and Humidity Dependent Reliability Analysis of RGB LED Chips

2006 ◽  
Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris
Keyword(s):  
Reliability Analysis ◽  
Printed Circuit Board ◽  
Light Emitting Diode ◽  
Circuit Board ◽  
Light Emitting ◽  
Printed Circuit ◽  
Root Cause ◽  
Micro Cracks ◽  
Temperature And Humidity

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.

scholarly journals Universal synthesis of conductive liquid network in polymers enabling elastic printed circuit board technology

2021 ◽  
Author(s):  
Jiheong Kang ◽  
Wonbeom Lee ◽  
Hyunjun Kim ◽  
Inho Kang ◽  
Hongjun Park ◽  
...  
Keyword(s):  
Liquid Metal ◽  
Acoustic Field ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
System Level ◽  
Large Strains ◽  
Stretchable Electronics ◽  
Electronic Components ◽  
Conductive Liquid ◽  
Printed Circuit

Abstract Stretchable electronics are considered next-generation electronic devices in a broad range of emerging fields, including soft robotics1,2, biomedical devices3,4, human-machine interfaces5,6, and virtual or augmented reality devices7,8. A stretchable printed circuit board (S-PCB) is a basic conductive framework for the facile assembly of system-level stretchable electronics with various electronic components. Since an S-PCB is responsible for electrical communications between numerous electronic components, the conductive lines in S-PCB should strictly satisfy the following features: (i) metallic conductivity, (ii) constant electrical resistance during dynamic stretching, and (iii) tough interface bonding with various components9. Despite recent significant advances in intrinsically stretchable conductors10,11,12, they cannot simultaneously satisfy the above stringent requirements. Here, we present a new concept of conductive liquid network-based elastic conductors. These conductors are based on unprecedented liquid metal particles assembled network (LMPNet) and an elastomer. The unique assembled network structure and reconfigurable nature of the LMPNet conductor enabled high conductivity, high stretchability, tough adhesion, and imperceptible resistance changes under large strains, which enabled the first elastic-PCB (E-PCB) technology. We synthesized LMPNet through an acoustic field-driven cavitation event in the solid state. When an acoustic field is applied, liquid metal nanoparticles (LMPnano) are remarkably generated from original LMPs and assemble into a highly conductive particle network (LMPNet). Finally, we demonstrated a multi-layered E-PCB, in which various electronic components were integrated with tough adhesion to form a highly stretchable health monitoring system. Since our synthesis of LMPNet is universal, we could synthesize LMPNet in various polymers, including hydrogel, self-healing elastomer and photoresist and add new functions to LMPNet.

Printed Circuit Board Propagating Faults

2004 ◽  
Author(s):  
Daren T. Slee
Keyword(s):  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Fault Tree Analysis ◽  
Circuit Board ◽  
Circuit Boards ◽  
Visual Examination ◽  
X Ray ◽  
Printed Circuit ◽  
Root Cause ◽  
X Ray Imaging

Abstract This paper is a review of propagating faults in printed circuit boards (PCBs) from the perspective of using the resulting burn and melted copper patterns to identify likely locations of fault initiation. Visual examination and x-ray imaging are the main techniques for examining PCB propagating faults. Once the likely fault initiation location has been identified, fault tree analysis can be used to determine the root cause for fault initiation. The paper discusses the mechanisms by which PCB propagating faults occur. The method of determining the likely area of initiation of the fault using visual examination of the PCB burn pattern, x-ray imaging, and the layout artwork for the PCB is discussed. The paper then goes on to discuss possible root-causes for the initiation of PCB propagating faults and some of their considerations.

A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000887-000892 ◽  
Author(s):  
Rudi Hechfellner ◽  
Michiel Kruger ◽  
Tewe Heemstra ◽  
Greg Caswell ◽  
Nathan Blattau ◽  
...  
Keyword(s):  
Solder Joint ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Light Emitting Diodes ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Control ◽  
Circuit Board ◽  
System Level ◽  
Light Emitting ◽  
Printed Circuit

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance. The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime. In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models. It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..

Effects of Trace Layers and Joule Heating on the Temperature Distribution of Printed Circuit Boards: A Computational Study

2009 ◽  
Vol 1 (2) ◽  
Author(s):  
M. Baris Dogruoz ◽  
Manoj K. Nagulapally
Keyword(s):  
Joule Heating ◽  
Hot Spots ◽  
Printed Circuit Board ◽  
Computational Study ◽  
Computational Cost ◽  
Circuit Board ◽  
System Level ◽  
Printed Circuit ◽  
System Level Simulation ◽  
Background Mesh

A printed circuit board (PCB) is generally a multilayered board made of dielectric material and several layers of traces and vias. Performing detailed system-level computational fluid dynamics (CFD) simulations of PCBs including meshed trace and via geometries for each of the layers is impractical. In the present approach, the effects of the trace and via geometry are accurately modeled in the physical model by importing electronics computer aided-design data consisting of the trace and via layout of the board and computing locally varying orthotropic conductivity (kx, ky, and kz) on the printed circuit board using a background mesh. The spatially varying orthotropic conductivity is then mapped from the background mesh to the CFD mesh and used in a system-level simulation of the PCB with a minimal increase in the overall computational cost. On the other hand, as PCB component densities increase, the current densities increase thereby leading to regions of hot spots due to Joule heating. Hence, it is essential that the computational heat transfer simulations account for the heating due to the high current carrying traces. In order to accurately model the Joule heating of traces and vias, it is of essence to solve for the conservation of current in each of these traces. In this study, the effects of both trace layer nonhomogeneity and Joule heating are examined on a sample PCB with several components attached to it. The results are then compared with those from the conventional modeling techniques. It is demonstrated that there is considerable difference in the location of the hot spots and temperature values between two different methods.

SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure

2021 ◽  
Vol 17 (3) ◽  
pp. 1-28
Author(s):  
Shubhra Deb Paul ◽  
Swarup Bhunia
Keyword(s):  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Supply Voltage ◽  
Semiconductor Industry ◽  
Electronic System ◽  
Circuit Board ◽  
System Level ◽  
Printed Circuit ◽  
Industry Standard ◽  
Custom Hardware

A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce SILVerIn , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (∼0.5%) hardware overhead. SILVerIn  is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup. SILVerIn  also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of ∼51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.

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