Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation

2018 ◽  
Author(s):  
Gaurav Rajavendra Reddy ◽  
Jin Wallner ◽  
Katherina Babich ◽  
Yiorgos Makris
Keyword(s):  
Pattern Matching ◽  
Integrated Circuit ◽  
Past Research ◽  
Silicon On Insulator ◽  
Advanced Technology ◽  
Ripple Effect ◽  
Matching Rule ◽  
Fully Depleted ◽  
Weak Points ◽  
The Impact

Abstract Continued technology scaling has led to exposure of many ‘weak-points’ in the designs fabricated in some of the most advanced technology nodes. Weak-points are certain layout patterns which are found to be sensitive to process non-idealities and have a higher tendency to cause defects. They may be coded in the form of Pattern Matching (PM) rules and included within the Design for Manufacturability Guidelines (DFMGs) to ensure product manufacturability. Often, during Integrated Circuit (IC) design, a trade-off is made between meeting performance specifications and complying with DFMGs. As a result, designs may reach the foundry with some DFMG violations. Fixing such violations generally causes a ‘ripple effect’ where one change requires many changes in other metal layers, making the process tedious. Therefore, providing a ranked list of guidelines to the designers helps them in assessing the criticality of violations, prioritizing, and fixing them accordingly. Past research suggests using diagnosis data to determine the impact of DFMG violations. However, this is a reactive approach wherein DFMGs are ranked only based on their hard-defect causing nature. To make the ranking process more robust, we propose a proactive silicon validation based approach which not only considers the yield loss due to hard-defects but also takes into account the parametric and reliability degradation caused by DFMG violations. We evaluate the effectiveness of the proposed methodology through on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node.

Effects of High–Energy Neutrons on Advanced SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 95-105 ◽  
Author(s):  
Valeriya Kilchytska ◽  
Joaquin Alvarado ◽  
Otilia Militaru ◽  
Guy Berger ◽  
Denis Flandre
Keyword(s):  
High Energy ◽  
Comparative Investigation ◽  
Silicon On Insulator ◽  
Dose Effect ◽  
Transient Effects ◽  
Short Channel ◽  
Flip Flop ◽  
Fully Depleted ◽  
Γ Rays ◽  
The Impact

This work discusses the degradations caused by high-energy neutrons in advanced MOSFETs and compares them with damages created by γ-rays reviewing the original researches performed in our laboratory during last years [1-6]. Fully–depleted (FD) Silicon-on-Insulator (SOI) MOSFETs and Multiple-Gate (MuG) FETs with different geometries (notably gate lengths down to 50 nm) have been considered. The impact of radiation on device behavior has been addressed through the variation of threshold voltage (VT), subthreshold slope (S), transconductance maximum (Gmmax) and drain-induced barrier lowering (DIBL). First, it is shown that degradations caused by high-energy neutrons in FD SOI and MuG MOSFETs are largely similar to that caused by γ-rays with similar doses [1,3]. Second, it is revealed that, contrarily to their generally-believed immunity to irradiation [7, 8], very short-channel MuGFETs with thin gate oxide can become extremely sensitive to the total dose effect [2,3]. The possible reason is proposed. Third, a comparative investigation of high-energy neutrons effects on strained and non-strained devices demonstrates a clear difference in their response to high-energy neutrons exposure [6]. Finally, based on simulations and modeling of partially –depleted (PD) SOI CMOS D Flip-Flop, we show how radiation-induced oxide charge and interface states build-up can affect well-known tolerance of SOI devices to transient effects [4,5].

MONTE-CARLO SIMULATION OF ULTRA-THIN FILM SILICON-ON-INSULATOR MOSFETs

2013 ◽  
Vol 22 (01) ◽  
pp. 1350001
Author(s):  
FRANCISCO GÁMIZ ◽  
CARLOS SAMPEDRO ◽  
LUCA DONETTI ◽  
ANDRES GODOY
Keyword(s):  
Monte Carlo ◽  
Ground Plane ◽  
Silicon On Insulator ◽  
Slab Thickness ◽  
Short Channel ◽  
Fully Depleted ◽  
Ensemble Monte Carlo ◽  
Soi Devices ◽  
Monte Carlo Simulator ◽  
The Impact

State-of-the-Art devices are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Ultrathin fully depleted Silicon-on-Insulator transistors and multi-gate devices based on SOI technology are the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials, substrate orientations and layer thicknesses to enhance the performance of CMOS circuits. From the point of view of simulation, these devices pose a significant challenge. Simulations tools have to include quantum effects in the whole structure to correctly describe the behavior of these devices. The Multi-Subband Monte Carlo (MSB-MC) approach constitutes today's most accurate method for the study of nanodevices with important applications to SOI devices. After reviewing the main basis of MSB-MC method, we have applied it to answer important questions which remain open regarding ultimate SOI devices. In the first part of the chapter we present a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin fully depleted SOI devices using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on short channel effects (SCEs). The simulations show that the main limiting factor for downscaling is the DIBL and the UTBOX+GP configuration is the only valid one to downscale SGSOI transistors beyond 20 nm channel length keeping the silicon slab thickness above the theoretical limit of 5 nm, where thickness variability and mobility reduction would play an important role. In the second part, we have used the multisubband Ensemble Monte Carlo simulator to study the electron transport in ultrashort DGSOI devices with different confinement and transport directions. Our simulation results show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

2017 ◽  
Vol 27 (04) ◽  
pp. 1850063 ◽  
Author(s):  
Rajneesh Sharma ◽  
Rituraj S. Rathore ◽  
Ashwani K. Rana
Keyword(s):  
Dielectric Materials ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
The Impact ◽  
Gate Underlap

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

scholarly journals Reduction in Crosstalk Using Uniform Germanium Strips for Dense Integration of Photonic Waveguides

2021 ◽  
Author(s):  
Veer Chandra ◽  
Dablu Kumar ◽  
Rakesh Ranjan
Keyword(s):  
Integrated Circuit ◽  
Silicon On Insulator ◽  
Current Work ◽  
Coupling Length ◽  
Photonic Integration ◽  
Polarization Splitter ◽  
Photonic Integrated Circuit ◽  
Photonic Switches ◽  
Photonic Waveguides ◽  
The Impact

Abstract The requirement of low crosstalk between the neighboring waveguides should be considered essentially, in order to achieve the compact photonic integrated circuit (PIC), which includes photonic waveguides. Literature shows that the lower crosstalk can be realized by using the silicon-on-insulator (SOI) based waveguide, having an appropriate separation between them. The current work is focused on reducing the waveguide separation to further improve the photonic integration over the PICs. This has been achieved by inserting the germanium strips between the photonic waveguides. The investigations of the impact of variations in heights and widths of germanium strip have demonstrated that the crosstalk can be reduced by a significant amount, which provides noteworthy improvement in coupling length. The maximum coupling lengths of 81578 µm, 67099 µm, and 66810 µm have been achieved at their respective end-to-end separations of 300 nm, 250 nm, and 200 nm, and their corresponding minimum crosstalk values have been noted as -29.40 dB, -27.71 dB, and − 27.70 dB. Moreover, the analysis to realize the coupling length for Ge-strip, have been compared with the Si-, and SiN-strips. The approach presented in the current work can be utilized for the design of many compact photonic applications, such as polarization splitter, integrated photonic switches, etc.

Beam Recrystallized Silicon-On-Insulator Devices

1981 ◽  
Vol 4 ◽  
Author(s):  
H. W. Lam
Keyword(s):  
Grain Boundaries ◽  
Integrated Circuit ◽  
Carrier Mobility ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Flat Panel Display ◽  
Enhanced Diffusion ◽  
Leakage Path ◽  
Short Circuits ◽  
The Impact

ABSTRACTBeam-recrystallized silicon-on-insulator is an attractive material for VLSI integrated circuit and flat panel display applications. This paper describes the electrical characteristics that are unique to MOSFETs fabricated in this material. The back-interface between the silicon and the insulator significantly affects the leakage current by acting as a possible leakage path, depending on the charge at the back interface and the doping concentration in the silicon close to the back interface. In addition, enhanced arsenic diffusion along grain boundaries can cause short circuits between the source and the drain of an n-channel MOSFET. Evidence of such enhanced diffusion are presented as well as means to reduce the impact of the problem. It is shown that molecular hydrogen can be used to passivate the grain-boundaries in the recrystallized silicon material, thereby increasing the carrier mobility. A profile of the carrier mobility as a function of depth from the surface of the silicon is presented, showing that the carrier mobility is not reduced significantly, even close to or at the back interface.

The Impact of Feature Packing Density on FIB Editing of Advanced Technology ICs

2003 ◽  
Author(s):  
H. Marchman ◽  
S. Herschbein ◽  
C. Scrudato ◽  
C. Rue ◽  
L. Fischer ◽  
...  
Keyword(s):  
Packing Density ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Advanced Technology ◽  
Reaction Products ◽  
Primary Sample ◽  
Deposition Processes ◽  
Upper Level ◽  
Lithographic Masks ◽  
The Impact

Abstract FIB techniques have provided a means for the nanometer-scale spatially confined etching and deposition processes required during repair or editing of advanced integrated circuit (IC) prototypes and lithographic masks. Primary sample properties that can lead to limitations on the applicability of FIB for IC repair are the material composition, aspect ratio, and feature packing density. The typical aims when developing a gas-assisted-etch (GAE) process for IC repair applications are enhancement of etch rate, increased volatilization of reaction products, and improved material selectivity. This paper presents results from a novel two-step process for clearing large areas of one micron thick (upper-level metal) layers. Better equalization of etch rates was achieved using the novel developed FIB GAE process. The paper describes the preliminary results obtained using non-gallium-ion beam based approaches for controlled surface modification during the editing of IC repair samples.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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