scholarly journals Reduction in Crosstalk Using Uniform Germanium Strips for Dense Integration of Photonic Waveguides

2021 ◽  
Author(s):  
Veer Chandra ◽  
Dablu Kumar ◽  
Rakesh Ranjan
Keyword(s):  
Integrated Circuit ◽  
Silicon On Insulator ◽  
Current Work ◽  
Coupling Length ◽  
Photonic Integration ◽  
Polarization Splitter ◽  
Photonic Integrated Circuit ◽  
Photonic Switches ◽  
Photonic Waveguides ◽  
The Impact

Abstract The requirement of low crosstalk between the neighboring waveguides should be considered essentially, in order to achieve the compact photonic integrated circuit (PIC), which includes photonic waveguides. Literature shows that the lower crosstalk can be realized by using the silicon-on-insulator (SOI) based waveguide, having an appropriate separation between them. The current work is focused on reducing the waveguide separation to further improve the photonic integration over the PICs. This has been achieved by inserting the germanium strips between the photonic waveguides. The investigations of the impact of variations in heights and widths of germanium strip have demonstrated that the crosstalk can be reduced by a significant amount, which provides noteworthy improvement in coupling length. The maximum coupling lengths of 81578 µm, 67099 µm, and 66810 µm have been achieved at their respective end-to-end separations of 300 nm, 250 nm, and 200 nm, and their corresponding minimum crosstalk values have been noted as -29.40 dB, -27.71 dB, and − 27.70 dB. Moreover, the analysis to realize the coupling length for Ge-strip, have been compared with the Si-, and SiN-strips. The approach presented in the current work can be utilized for the design of many compact photonic applications, such as polarization splitter, integrated photonic switches, etc.

Design and characteristics of reflectivity tunable mirror with MZI and loop waveguide on SOI

2021 ◽  
Author(s):  
Yutaka Makihara ◽  
Moataz Eissa ◽  
Tomohiro AMEMIYA ◽  
Nobuhiko Nishiyama
Keyword(s):  
Phase Shift ◽  
Coupling Coefficient ◽  
Integrated Circuit ◽  
Silicon Photonics ◽  
Silicon On Insulator ◽  
Zehnder Interferometer ◽  
Directional Couplers ◽  
Photonic Integrated Circuit ◽  
Active Elements ◽  
Measurement Results

Abstract To achieve a reconfigurable photonic integrated circuit with active elements, we proposed a reflectivity tunable mirror constructed using a Mach–Zehnder interferometer (MZI) with a micro heater and loop waveguide on a silicon photonics platform. In this paper, the principle of the operation, design, fabrication, and measurement results of the mirror are presented. In theory, the phase shift dependence of the mirror relies on the coupling coefficient of the directional couplers of the MZI. When the coupling coefficient κ2 was 0.5 and 0.15, the reflection could be turned on and off with a phase shift of π/2 and π, respectively. The reflection power of the fabricated mirror on the silicon on insulator (SOI) substrate was changed by more than 20 dB by a phase shift. In addition, it was demonstrated that the phase shift dependence of the mirror changes with the coupling coefficient of the fabricated devices.

Thermodynamic insights into Henry's constant in hyperthermal oxidation of silicon for fabricating optical waveguides

2021 ◽  
Author(s):  
Ting Yu ◽  
DeGui Sun
Keyword(s):  
Integrated Circuit ◽  
Optical Waveguides ◽  
Silicon On Insulator ◽  
Henry's Constant ◽  
Photonic Integrated Circuit ◽  
Local Oxidation ◽  
Waveguide Fabrication

Hyperthermal oxidation of silicon is envisaged to be an alternative to silicon-on-insulator (SOI) waveguide fabrication for photonic integrated circuit (PIC) devices, and thus the local oxidation of silicon (LOCOS) technique has attracted attention.

Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation

2018 ◽  
Author(s):  
Gaurav Rajavendra Reddy ◽  
Jin Wallner ◽  
Katherina Babich ◽  
Yiorgos Makris
Keyword(s):  
Pattern Matching ◽  
Integrated Circuit ◽  
Past Research ◽  
Silicon On Insulator ◽  
Advanced Technology ◽  
Ripple Effect ◽  
Matching Rule ◽  
Fully Depleted ◽  
Weak Points ◽  
The Impact

Abstract Continued technology scaling has led to exposure of many ‘weak-points’ in the designs fabricated in some of the most advanced technology nodes. Weak-points are certain layout patterns which are found to be sensitive to process non-idealities and have a higher tendency to cause defects. They may be coded in the form of Pattern Matching (PM) rules and included within the Design for Manufacturability Guidelines (DFMGs) to ensure product manufacturability. Often, during Integrated Circuit (IC) design, a trade-off is made between meeting performance specifications and complying with DFMGs. As a result, designs may reach the foundry with some DFMG violations. Fixing such violations generally causes a ‘ripple effect’ where one change requires many changes in other metal layers, making the process tedious. Therefore, providing a ranked list of guidelines to the designers helps them in assessing the criticality of violations, prioritizing, and fixing them accordingly. Past research suggests using diagnosis data to determine the impact of DFMG violations. However, this is a reactive approach wherein DFMGs are ranked only based on their hard-defect causing nature. To make the ranking process more robust, we propose a proactive silicon validation based approach which not only considers the yield loss due to hard-defects but also takes into account the parametric and reliability degradation caused by DFMG violations. We evaluate the effectiveness of the proposed methodology through on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node.

Footprint Analysis of CMOS Compatible Silicon-on-Insulator based Photonic Waveguides

2020 ◽  
Vol 12 ◽  
Author(s):  
Veer Chandra ◽  
Rakesh Ranjan
Keyword(s):  
Silicon On Insulator ◽  
Propagation Loss ◽  
Comsol Multiphysics ◽  
The Finite Element Method ◽  
Propagation Length ◽  
Footprint Analysis ◽  
Photonic Waveguides ◽  
Cmos Compatible ◽  
The Impact ◽  
Slot Waveguides

Aim: Establish the efficient footprint size, i.e., the total substrate width of photonic waveguides (Ridge, Rib, and Slot) under the fundamental mode propagation constraints. Objective: By varying the total substrate width for all photonic waveguides (Ridge, Rib, and Slot) with respect to four major waveguide parameters, namely effective refractive index, propagation loss, propagation length, and confinement percentage, the converged values of these waveguide parameters have to be obtained. Methods: The finite element method (FEM) based simulations, using the COMSOL Multiphysics, have been used to study the modal characteristics of photonic waveguides to achieve their efficient footprint size. Results: The total substrate widths have been obtained for the all four parameters and considering the impact of all these waveguide parameters simultaneously, the efficient total substrate width have been recognized as 2500 nm, 4000 nm, and 3000 nm, respectively for Ridge, Rib, and Slot waveguides. Conclusion: The efficient waveguide footprints, i.e., the total substrate widths for the three photonic waveguides, namely Ridge, Rib and Slot waveguides have been established.

scholarly journals Broadband Terahertz Photonic Integrated Circuit with Integrated Active Photonic Devices

Photonics ◽  
2021 ◽  
Vol 8 (11) ◽  
pp. 492
Author(s):  
Amlan kusum Mukherjee ◽  
Mingjun Xiang ◽  
Sascha Preu
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Near Field ◽  
Single Mode ◽  
Silicon On Insulator ◽  
High Resistivity ◽  
Active Components ◽  
Photonic Integrated Circuit ◽  
Active Devices ◽  
Frequency Coverage

Present-day photonic terahertz (100 GHz–10 THz) systems offer dynamic ranges beyond 100 dB and frequency coverage beyond 4 THz. They yet predominantly employ free-space Terahertz propagation, lacking integration depth and miniaturisation capabilities without sacrificing their extreme frequency coverage. In this work, we present a high resistivity silicon-on-insulator-based multimodal waveguide topology including active components (e.g., THz receivers) as well as passive components (couplers/splitters, bends, resonators) investigated over a frequency range of 0.5–1.6 THz. The waveguides have a single mode bandwidth between 0.5–0.75 THz; however, above 1 THz, these waveguides can be operated in the overmoded regime offering lower loss than commonly implemented hollow metal waveguides, operated in the fundamental mode. Supported by quartz and polyethylene substrates, the platform for Terahertz photonic integrated circuits (Tera-PICs) is mechanically stable and easily integrable. Additionally, we demonstrate several key components for Tera-PICs: low loss bends with radii ∼2 mm, a Vivaldi antenna-based efficient near-field coupling to active devices, a 3-dB splitter and a filter based on a whispering gallery mode resonator.

Beam Recrystallized Silicon-On-Insulator Devices

1981 ◽  
Vol 4 ◽  
Author(s):  
H. W. Lam
Keyword(s):  
Grain Boundaries ◽  
Integrated Circuit ◽  
Carrier Mobility ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Flat Panel Display ◽  
Enhanced Diffusion ◽  
Leakage Path ◽  
Short Circuits ◽  
The Impact

ABSTRACTBeam-recrystallized silicon-on-insulator is an attractive material for VLSI integrated circuit and flat panel display applications. This paper describes the electrical characteristics that are unique to MOSFETs fabricated in this material. The back-interface between the silicon and the insulator significantly affects the leakage current by acting as a possible leakage path, depending on the charge at the back interface and the doping concentration in the silicon close to the back interface. In addition, enhanced arsenic diffusion along grain boundaries can cause short circuits between the source and the drain of an n-channel MOSFET. Evidence of such enhanced diffusion are presented as well as means to reduce the impact of the problem. It is shown that molecular hydrogen can be used to passivate the grain-boundaries in the recrystallized silicon material, thereby increasing the carrier mobility. A profile of the carrier mobility as a function of depth from the surface of the silicon is presented, showing that the carrier mobility is not reduced significantly, even close to or at the back interface.

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