Beam Recrystallized Silicon-On-Insulator Devices

MRS Proceedings ◽

10.1557/proc-4-471 ◽

1981 ◽

Vol 4 ◽

Author(s):

H. W. Lam

Keyword(s):

Grain Boundaries ◽

Integrated Circuit ◽

Carrier Mobility ◽

Silicon On Insulator ◽

Electrical Characteristics ◽

Flat Panel Display ◽

Enhanced Diffusion ◽

Leakage Path ◽

Short Circuits ◽

The Impact

ABSTRACTBeam-recrystallized silicon-on-insulator is an attractive material for VLSI integrated circuit and flat panel display applications. This paper describes the electrical characteristics that are unique to MOSFETs fabricated in this material. The back-interface between the silicon and the insulator significantly affects the leakage current by acting as a possible leakage path, depending on the charge at the back interface and the doping concentration in the silicon close to the back interface. In addition, enhanced arsenic diffusion along grain boundaries can cause short circuits between the source and the drain of an n-channel MOSFET. Evidence of such enhanced diffusion are presented as well as means to reduce the impact of the problem. It is shown that molecular hydrogen can be used to passivate the grain-boundaries in the recrystallized silicon material, thereby increasing the carrier mobility. A profile of the carrier mobility as a function of depth from the surface of the silicon is presented, showing that the carrier mobility is not reduced significantly, even close to or at the back interface.

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Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation

10.31399/asm.cp.istfa2018p0443 ◽

2018 ◽

Author(s):

Gaurav Rajavendra Reddy ◽

Jin Wallner ◽

Katherina Babich ◽

Yiorgos Makris

Keyword(s):

Pattern Matching ◽

Integrated Circuit ◽

Past Research ◽

Silicon On Insulator ◽

Advanced Technology ◽

Ripple Effect ◽

Matching Rule ◽

Fully Depleted ◽

Weak Points ◽

The Impact

Abstract Continued technology scaling has led to exposure of many ‘weak-points’ in the designs fabricated in some of the most advanced technology nodes. Weak-points are certain layout patterns which are found to be sensitive to process non-idealities and have a higher tendency to cause defects. They may be coded in the form of Pattern Matching (PM) rules and included within the Design for Manufacturability Guidelines (DFMGs) to ensure product manufacturability. Often, during Integrated Circuit (IC) design, a trade-off is made between meeting performance specifications and complying with DFMGs. As a result, designs may reach the foundry with some DFMG violations. Fixing such violations generally causes a ‘ripple effect’ where one change requires many changes in other metal layers, making the process tedious. Therefore, providing a ranked list of guidelines to the designers helps them in assessing the criticality of violations, prioritizing, and fixing them accordingly. Past research suggests using diagnosis data to determine the impact of DFMG violations. However, this is a reactive approach wherein DFMGs are ranked only based on their hard-defect causing nature. To make the ranking process more robust, we propose a proactive silicon validation based approach which not only considers the yield loss due to hard-defects but also takes into account the parametric and reliability degradation caused by DFMG violations. We evaluate the effectiveness of the proposed methodology through on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node.

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Characteristics of Short-Channel Mosfet's in Laser Crystallized Si-on-Insulator

MRS Proceedings ◽

10.1557/proc-23-559 ◽

1983 ◽

Vol 23 ◽

Author(s):

K. K. Ng ◽

G. K. Celler ◽

E. I. Povilonis ◽

L. E. Trimble ◽

S. M. Sze

Keyword(s):

Low Temperature ◽

Grain Boundaries ◽

Bulk Material ◽

Silicon On Insulator ◽

Ring Oscillators ◽

Short Channel ◽

Furnace Annealing ◽

Enhanced Diffusion ◽

Channel Lengths ◽

Temperature Furnace

ABSTRACTData are reported on short-channel MOSFET's fabricated in laser crystallized silicon-on-insulator (SOI) structures. In this experiment, special effort was made to minimize enhanced diffusion of dopants from the source and drain regions along grain boundaries. Instead of the standard anneal used for the implant activation, rapid thermal annealing and low temperature furnace annealing were used. These modified processes yielded functional MOSFET's with channel lengths as short as 1.5 μm, and ring oscillators of 2.0 μm. A speed of 115 ps per stage was obtained in these ring oscillators which is not only the fastest ever reported on any SOI structure, but also a factor of 2 faster than that from the same circuits in bulk Si. The results demonstrate quantitatively the speed improvement of SOI over bulk material due to reduced parasitic capacitance.

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Reduction in Crosstalk Using Uniform Germanium Strips for Dense Integration of Photonic Waveguides

10.21203/rs.3.rs-714338/v1 ◽

2021 ◽

Author(s):

Veer Chandra ◽

Dablu Kumar ◽

Rakesh Ranjan

Keyword(s):

Integrated Circuit ◽

Silicon On Insulator ◽

Current Work ◽

Coupling Length ◽

Photonic Integration ◽

Polarization Splitter ◽

Photonic Integrated Circuit ◽

Photonic Switches ◽

Photonic Waveguides ◽

The Impact

Abstract The requirement of low crosstalk between the neighboring waveguides should be considered essentially, in order to achieve the compact photonic integrated circuit (PIC), which includes photonic waveguides. Literature shows that the lower crosstalk can be realized by using the silicon-on-insulator (SOI) based waveguide, having an appropriate separation between them. The current work is focused on reducing the waveguide separation to further improve the photonic integration over the PICs. This has been achieved by inserting the germanium strips between the photonic waveguides. The investigations of the impact of variations in heights and widths of germanium strip have demonstrated that the crosstalk can be reduced by a significant amount, which provides noteworthy improvement in coupling length. The maximum coupling lengths of 81578 µm, 67099 µm, and 66810 µm have been achieved at their respective end-to-end separations of 300 nm, 250 nm, and 200 nm, and their corresponding minimum crosstalk values have been noted as -29.40 dB, -27.71 dB, and − 27.70 dB. Moreover, the analysis to realize the coupling length for Ge-strip, have been compared with the Si-, and SiN-strips. The approach presented in the current work can be utilized for the design of many compact photonic applications, such as polarization splitter, integrated photonic switches, etc.

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Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2015p0154 ◽

2015 ◽

Author(s):

Halit Dogan ◽

Md Mahbub Alam ◽

Navid Asadizanjani ◽

Sina Shahbazmohamadi ◽

Domenic Forte ◽

...

Keyword(s):

Integrated Circuits ◽

Integrated Circuit ◽

3D Imaging ◽

Three Dimensional ◽

Serial Sectioning ◽

Promising Technique ◽

Flash Memories ◽

X Ray ◽

3D Information ◽

The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

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A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0172 ◽

2007 ◽

Author(s):

Hung-Sung Lin ◽

Ying-Chin Hou ◽

Juimei Fu ◽

Mong-Sheng Wu ◽

Vincent Huang ◽

...

Keyword(s):

Liquid Crystal ◽

Circuit Design ◽

Process Design ◽

Integrated Circuit ◽

Photon Emission ◽

Integrated Circuit Design ◽

Nano Scale ◽

Leakage Path ◽

Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

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An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

Nanoscience &Nanotechnology-Asia ◽

10.2174/2210681208666180820151121 ◽

2019 ◽

Vol 9 (4) ◽

pp. 504-511

Author(s):

Sikha Mishra ◽

Urmila Bhanja ◽

Guru Prasad Mishra

Keyword(s):

Analytical Model ◽

Surface Potential ◽

Threshold Voltage ◽

Silicon On Insulator ◽

Junction Depth ◽

Short Channel ◽

Soi Mosfet ◽

Minimum Surface ◽

Recessed Channel ◽

The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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