Capacitance Characterization of Gate to LDD Overlap Region to Understand Subtle Fail Modes in Advanced Node Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Edmund Banghart ◽  
Kevin Davidson ◽  
Yu Zhang ◽  
Jagar Singh ◽  
...  
Keyword(s):  
Work Function ◽  
Case Studies ◽  
Failure Mode ◽  
Defect Mode ◽  
Device Under Test ◽  
Root Cause ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Lightly Doped Drain

Abstract This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

2007 ◽  
Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel
Keyword(s):  
Failure Mode ◽  
Failure Modes ◽  
Fault Modeling ◽  
Mode Analysis ◽  
Root Cause ◽  
Failure Mode Analysis

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

Low Voltage, Low Current AFP Characterization of Non-Visible Soft Transistor Defects

2008 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Case Studies ◽  
Computer Aided Design ◽  
Low Voltage ◽  
Process Analysis ◽  
Failure Mechanisms ◽  
Electrical Characterization ◽  
Manufacturing Facility ◽  
Root Cause ◽  
Aided Design

Abstract This paper presents case studies that examine low voltage, low current electrical characterization and analysis of data that could help identify root cause failure mechanisms for soft transistor failures, providing a review of Vt shifts and blocked LDD implants review. The case studies demonstrate the importance of getting the most information possible out of all aspects of the nanoprobe electrical characterization results for failing transistors. Technology computer aided design (TCAD) modeling of transistor defects will be a useful tool for the nanoprobe analyst to identify the subtle defects that can only be identified through careful electrical characterization in conjunction with process analysis and experiments by the manufacturing facility. However, modeling at the transistor level has its difficulties. The key will be to build a library of electrical signatures with corresponding defects as they are discovered.

Characterization of the SiO2/SiC Interface with Impedance Spectroscopy

2009 ◽  
Vol 615-617 ◽  
pp. 501-504 ◽  
Author(s):  
Pawel A. Sobas ◽  
Ulrike Grossner ◽  
Bengt Gunnar Svensson
Keyword(s):  
Impedance Spectroscopy ◽  
Ionic Conduction ◽  
Semiconductor Interface ◽  
Transfer Processes ◽  
Capacitance Voltage ◽  
Dc Bias ◽  
The One ◽  
Cv Measurements ◽  
Mos Structures

Using impedance spectroscopy (IS) for the characterization of SiO2/4H-SiC (MOS) structures, insight on the capacitive and resistive contributions in different physical regions of the MOS structures is obtained. Changing the DC bias conditions, semiconductor, interface as well as oxide traps can be detected. The MOS capacitance, as extracted from IS data, is different from the one obtained using capacitance voltage (CV) measurements, due to the possibility of distinguishing different charge transfer processes using IS. For instance, in the investigated capacitors, a clear contribution is revealed from ionic conduction processes at bias voltages close to zero.

Interpreting Laser-Based Fault Localization Results: Case Studies

2019 ◽  
Author(s):  
Sukho Lee ◽  
John van den Biggelaar ◽  
Marc van Veenhuizen
Keyword(s):  
Case Studies ◽  
Circuit Design ◽  
High Sensitivity ◽  
Failure Behavior ◽  
Process Technology ◽  
Resistance Change ◽  
Voltage Imaging ◽  
Root Cause ◽  
First Case ◽  
Proper Interpretation

Abstract Laser-based dynamic analysis has become a very important tool for analyzing advanced process technology and complex circuit design. Thus, many good reference papers discuss high resolution, high sensitivity, and useful applications. However, proper interpretation of the measurement is important as well to understand the failure behavior and find the root cause. This paper demonstrates this importance by describing two insightful case studies with unique observations from laser voltage imaging/laser voltage probing (LVP), optical beam induced resistance change, and soft defect localization (SDL) analysis, which required an in-depth interpretation of the failure analysis (FA) results. The first case is a sawtooth LVP signal induced by a metal short. The second case, a mismatched result between an LVP and SDL analysis, is a good case of unusual LVP data induced by a very sensitive response to laser light. The two cases provide a good reference on how to properly explain FA results.

Contamination Troubleshooting Approach from Problem to Solution

2019 ◽  
Author(s):  
Victor K. F. Chia ◽  
Hugh E. Gotts ◽  
Fuhe Li ◽  
Mark Camenzind
Keyword(s):  
Case Studies ◽  
Semiconductor Devices ◽  
Analytical Techniques ◽  
General Knowledge ◽  
Contamination Source ◽  
Root Cause ◽  
Sources Of Contamination

Abstract Semiconductor devices are sensitive to contamination that can cause product defects and product rejects. There are many possible types and sources of contamination. Root cause resolution of the contamination source can improve yield. The purpose of contamination troubleshooting is to identify and eliminate major yield limiters. This requires the use of a variety of analytical techniques[1]. Most important, it requires an understanding of the principle of contamination troubleshooting and general knowledge of analytical tests. This paper describes a contamination troubleshooting approach with case studies as examples of its application.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

2013 ◽  
Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
Case Studies ◽  
State Of The Art ◽  
Root Cause ◽  
Highly Efficient ◽  
Technology Nodes ◽  
Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

SEM/EDS Characterization of Uncommon Metal Whiskers and Determination of Underlying Growth Mechanisms

2018 ◽  
Author(s):  
D. Basak ◽  
L. H. Ponce
Keyword(s):  
Reliability Analysis ◽  
Case Studies ◽  
Whisker Growth ◽  
Innovation Systems ◽  
Growth Mechanisms ◽  
Crystal Oscillator ◽  
Analysis Laboratory ◽  
Investigative Techniques

Abstract Two case-studies on uncommon metals whiskers, performed at the Reliability Analysis Laboratory (RAL) of Northrop Grumman Innovation Systems, are presented. The components analyzed are an Oven Controlled Crystal Oscillator (OCXO) and an Electromechanical Relay. Investigative techniques were used to determine the chemical and physical makeup of the metal whiskers and develop an understanding of the underlying effects and mechanisms that caused the conditions conducive to whisker growth.

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