scholarly journals Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

2021 ◽  
pp. 07-24
Author(s):  
Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Logic Gate ◽  
Clear Understanding ◽  
Threshold Logic ◽  
Xor Gate ◽  
Multiple Input ◽  
Exclusive Or ◽  
Hypercube Network ◽  
Or Gate

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.

scholarly journals An Accumulator using Electron Tunneling Through Tunnel Junction

2021 ◽  
pp. 163-183
Author(s):  
Dr. Anup Kumar Biswas
Keyword(s):  
High Speed ◽  
Electron Tunneling ◽  
Low Cost ◽  
Logic Gate ◽  
Logic Gates ◽  
Threshold Logic ◽  
High Concentration ◽  
Flip Flop ◽  
Linear Threshold ◽  
Parameter Values

Instead of an existing logical Technology, by using an emerging technology we will be able to make an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is based on the linear threshold logic condition and electron-tunneling event. At the time of implementing a circuit, a multi-inputs but one-output based logic-node will be brought in our consideration. In this work, we have designed a 1-bit accumulator and then implemented it. To develop an accumulator, some small components like 2-input AND, 3-input AND, 3-input OR, 8-input OR, 9-input OR gate and above all a JK Flip-flop (for 1-bit) are to be collected and connected them in logical order to obtain the proper circuit. After verifying all their characteristics with the results obtained from the simulator, we have built a 1-bit accumulator. All the small components are provided in due places. They are analyzed, detected their threshold logic equations, shown their threshold logic gates (TLGs), tabulated their truth tables, drawn their input-output waveforms, given their respective circuits with exact parameter values. In the accumulator, there are nine control variables S1 through S9 in view of performing the operations (i) Addition, (ii) clear, (iii) complement, (iv) AND, (v) OR, (vi) XOR, (vii) Right-shift, (viii) Left-shift and (ix) increment with positive triggering clock pulses. Whether our present work’s circuits are faster or slower with respect to the similar circuits of CMOS based- and Single electron transistor (SET) based circuits are compared and observed that our TLG based circuits are faster than the CMOS and SET based circuits. The power consumed for tunneling event for a circuit is measured and sensed that it would remain in the range of 10meV to 250meV which is low. All the circuits we have presented in this work are of ‘generic multiple input threshold logic gate’ which is elaborately discussed.

Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sadat Riyaz ◽  
Vijay Kumar Sharma
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Cell Count ◽  
High Speed ◽  
Xor Gate ◽  
Content Type ◽  
Quantum Dot Cellular Automata ◽  
Logical Operations ◽  
Feynman Gate ◽  
Exclusive Or

Purpose This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency. Design/methodology/approach The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology. Findings QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones. Originality/value The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.

scholarly journals The Design of Low-Power High-Speed Two-Level Three Input XOR gate

2020 ◽  
Vol 9 (5) ◽  
pp. 1813-1818
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Signal Frequency ◽  
Xor Gate ◽  
Input Signal Frequency ◽  
Transmission Gates ◽  
Exclusive Or

The Large Fan-In and high performance gates are essential to make portable electronic devices. In this paper an efficient realization of three input two level XOR(Exclusive-OR) is presented. The design of low power and high speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. Two methods were used to design proposed XOR, one (i.e. Pass_gate) is purely based on pass transistors with 8 MOSFET’s and second method(Modified_Pass_gate) uses transmission gates with 12 transistors. The Modified_Pass_gate offers 86.14% and 6.66% of power dissipation reduction compared to static and Pass_gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool.

All Optical High Speed Multiplexer Circuit for Verification of Proposed Gates

2018 ◽  
Vol 39 (3) ◽  
pp. 289-295
Author(s):  
Pawan Chanalia ◽  
Amit Gupta ◽  
Shaina ◽  
Surbhi Bakshi
Keyword(s):  
Optical Communication ◽  
Data Streams ◽  
Phase Modulation ◽  
High Speed ◽  
Logic Gate ◽  
Optical Coupler ◽  
Successful Operation ◽  
Xor Gate ◽  
All Optical ◽  
Generation Information

Abstract An all optical communication is fast and reliable for next generation information carrying systems. For successful operation of fast data over flexible transmission line is only possible by all optical multiplexer and can serve for network. A 60 Gbps all optical multiplexer using cheap components has been realized and also tested on different speeds of input data streams. For integral and flexible multiplexer, optical semiconductor-based MZI switch taken into consideration. MZI-SOA is used to generate two logical gates outputs such as (AND)(XOR) gate. Multiplexer working is based on SOA nonlinearity properties and optical coupler. XOR logic gate contingent on cross-phase modulation in amplifier and logic AND for four-wave mixing is obtained from cross port and bar port respectively. Simulation is performed and multiplexer is tested for different launched power in tree architecture. System performance indicates that it can work for high speed (60 Gbps) and different data entities.

Low power, high speed, charge recycling CMOS threshold logic gate

2001 ◽  
Vol 37 (17) ◽  
pp. 1067 ◽  
Author(s):  
P. Celinski ◽  
J.F. López ◽  
S. Al-Sarawi ◽  
D. Abbott
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gate ◽  
Threshold Logic ◽  
Charge Recycling

Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata

2019 ◽  
Vol 28 (08) ◽  
pp. 1950141 ◽  
Author(s):  
Haotian Chen ◽  
Hongjun Lv ◽  
Zhang Zhang ◽  
Xin Cheng ◽  
Guangjun Xie
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Simulation Analysis ◽  
Clock Cycle ◽  
Performance Comparison ◽  
Xor Gate ◽  
Quantum Dot Cellular Automata ◽  
Exclusive Or ◽  
Or Gate

Recently reported quantum-dot cellular automata (QCA) exclusive-OR gate designs are usually made with the AND–OR–INVERTER method in which it is difficult to optimize the XOR gate. This paper presents a novel low-power exclusive-OR (XOR) gate which is mainly based on cell-level format. Compared with the previous XOR gates, the proposed XOR gate performs in a different manner. This XOR gate design is accomplished by the intercellular effects method. For better performance comparison with previous relevant works, 4-, 8-, 16- and 32-bit parity generators are implemented in this paper. The simulation results show that there is a reduction of 32.5% cell count and 21.5% area in comparison with the existing advanced 32-bit parity generator. Especially in the aspect of clock cycle, the proposed design reduces the delay by 50% compared to the previous design. For simulation analysis, QCADesigner tool is used to verify the correctness of the proposed design. QCApro tool is used to evaluate the power dissipation of this design.

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

2015 ◽  
Vol 24 (05) ◽  
pp. 1550073 ◽  
Author(s):  
Vikas Mahor ◽  
Manisha Pattanaik
Keyword(s):  
High Speed ◽  
Noise Immunity ◽  
Logic Gate ◽  
Dynamic Logic ◽  
Critical Issue ◽  
Low Noise ◽  
Back Gate ◽  
High Noise ◽  
Low Leakage ◽  
Or Gate

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

High speed GaAs optoelectronic exclusive-OR gate

1994 ◽  
Vol 30 (1) ◽  
pp. 81-83 ◽  
Author(s):  
T.C. She ◽  
C. Shu
Keyword(s):  
High Speed ◽  
Exclusive Or ◽  
Or Gate
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