scholarly journals Time-interleaved pulse-shrinking and all-digital time-to-digital converters

2021 ◽  
Author(s):  
Young Jun Park
Keyword(s):  
Time Resolution ◽  
Dynamic Range ◽  
Time Integration ◽  
Cmos Technology ◽  
Noise Shaping ◽  
Residual Time ◽  
Measurement Results ◽  
Conversion Time ◽  
Simulation Results ◽  
Time Interleaved

This dissertation deals with the design of sub-per-stage delay time-to-digital converters (TDCs). Two classes of TDCs namely pulse-shrinking TDCs and TDCs are investigated. In pulse-shrinking TDCs, a two-step pulse-shrinking TDC consisting of a set of coarse and fine pulse-shrinking TDCs is proposed to increase a dynamic range without employing a large number of pulse-shrinking stages. A residual time extraction scheme capable of extracting the residual time of the coarse TDC is developed. The simulation / measurement results of the TDC implemented in an IBM 130 nm 1.2 V CMOS technology show that the TDC offers 1.4 ns conversion time, 1LSB DNL and INL, and consumes 0.163 pJ/step. To further improve the conversion time, a time-interleaved scheme is developed to extract the residual time of the coarse TDC and utilized in design of a two-step pulse-shrinking TDC. Residual time extraction is carried out in parallel with digitization of minimize latency. The simulation and measurement results of the TDC show that is offers 0.85 ns conversion time, 0.285 LSB DNL, and 0.78 LSB. In TDCs, a 1-1 multi-stage noise shaping (MASH) TDC with a new differential cascode time integrator is proposed to suppress even-order harmonic tones and current mismatch-induced timing errors. Simulation results show that the proposed TDC offers 1.9 ps time resolution over 48-415 kHz signal band with consuming 5-2 uW. Finally , an all-digital first-order TDC utilizing a bi-directional gated delay line integrator is developed. Time integration is obtained via the accumulation of charge of the load capacitor of gated delay stages and the logic state of gated delay stages. The elimination of analog components allows the TDC to benefit fully from technology scaling. Simulation results show that the TDC offers firs-order noise-shaping, 10.8 ps time resolution while consuming 46 uW.

scholarly journals Time-interleaved pulse-shrinking and all-digital time-to-digital converters

2021 ◽  
Author(s):  
Young Jun Park
Keyword(s):  
Time Resolution ◽  
Dynamic Range ◽  
Time Integration ◽  
Cmos Technology ◽  
Noise Shaping ◽  
Residual Time ◽  
Measurement Results ◽  
Conversion Time ◽  
Simulation Results ◽  
Time Interleaved

This dissertation deals with the design of sub-per-stage delay time-to-digital converters (TDCs). Two classes of TDCs namely pulse-shrinking TDCs and TDCs are investigated. In pulse-shrinking TDCs, a two-step pulse-shrinking TDC consisting of a set of coarse and fine pulse-shrinking TDCs is proposed to increase a dynamic range without employing a large number of pulse-shrinking stages. A residual time extraction scheme capable of extracting the residual time of the coarse TDC is developed. The simulation / measurement results of the TDC implemented in an IBM 130 nm 1.2 V CMOS technology show that the TDC offers 1.4 ns conversion time, 1LSB DNL and INL, and consumes 0.163 pJ/step. To further improve the conversion time, a time-interleaved scheme is developed to extract the residual time of the coarse TDC and utilized in design of a two-step pulse-shrinking TDC. Residual time extraction is carried out in parallel with digitization of minimize latency. The simulation and measurement results of the TDC show that is offers 0.85 ns conversion time, 0.285 LSB DNL, and 0.78 LSB. In TDCs, a 1-1 multi-stage noise shaping (MASH) TDC with a new differential cascode time integrator is proposed to suppress even-order harmonic tones and current mismatch-induced timing errors. Simulation results show that the proposed TDC offers 1.9 ps time resolution over 48-415 kHz signal band with consuming 5-2 uW. Finally , an all-digital first-order TDC utilizing a bi-directional gated delay line integrator is developed. Time integration is obtained via the accumulation of charge of the load capacitor of gated delay stages and the logic state of gated delay stages. The elimination of analog components allows the TDC to benefit fully from technology scaling. Simulation results show that the TDC offers firs-order noise-shaping, 10.8 ps time resolution while consuming 46 uW.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes

Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 372 ◽  
Author(s):  
Risheng Lv ◽  
Weiping Chen ◽  
Xiaowei Liu
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
High Dynamic Range ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Multi Stage ◽  
Sigma Delta Adc

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

A Low-Cost RFID Regulator Insensitive to Temperature and Supply Voltage Variations

2017 ◽  
Vol 26 (10) ◽  
pp. 1750153
Author(s):  
Dawei Li ◽  
Dongsheng Liu ◽  
Xuecheng Zou ◽  
Ke Yao ◽  
Chaojian Kang ◽  
...  
Keyword(s):  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Low Cost ◽  
Cmos Technology ◽  
Rejection Ratio ◽  
Supply Noise ◽  
Measurement Results ◽  
Frequency Identification ◽  
Simulation Results ◽  
Long Channel

A low-cost regulator insensitive to temperature and supply voltage variations for power management units of Radio Frequency Identification (RFID) tag chips and other batteryless devices is proposed in this paper. The commonly used regulator has poor temperature rejection ratio (TRR) and poor voltage rejection ratio (VRR). By using combination resistors and long channel transistors, the bias and regulator circuits are improved over temperature variations. A power supply rejection (PSR) enhancement branch is also added to suppress the supply noise and stabilize the bias current. The regulator is designed and fabricated in the HJTC 0.25[Formula: see text][Formula: see text]m CMOS technology. Simulation results show that this regulator achieves 0.044[Formula: see text]mV/[Formula: see text]C TRR when temperature varies from [Formula: see text]C to 70[Formula: see text]C and 1.1[Formula: see text]mV/V VRR while the supply voltage of the regulator ranges from 4 to 12[Formula: see text]V. The PSR is nearly [Formula: see text]100[Formula: see text]dB at DC. The area of this regulator is 0.102[Formula: see text]mm2 including the bias circuit. The measurement results meet simulation results well and this regulator is successfully applied in HF passive tag chips within voltage deviations of [Formula: see text] of 2.5[Formula: see text]V.

scholarly journals Time-mode signal processing and application in ΔΣ ADC design

2021 ◽  
Author(s):  
Guangyu Zhu
Keyword(s):  
Dynamic Range ◽  
Building Blocks ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Noise Shaping ◽  
Loop Filter ◽  
Linear Effect ◽  
Circuit Components ◽  
Δσ Adc ◽  
Time Amplifier

An all-digitally implemented 1st order and a 2nd order time-mode ΔΣ ADCs are proposed and presented in this dissertation. Each proposed ΔΣ ADC consists of a voltage-to- time integration converter, a seven-stage gated ring oscillator functioning as a 3-bit quantizer, and a 7-stage digital differentiator that provides noise-shaping and frequency feedback. The 2nd order architecture differs from the 1st order by cascading two digital differentiators. The 2nd order design improves noise-shaping characteristic and SNDR. However it does not effectively suppress the harmonic tones due to the non-linear effect of the circuit components. Thus a detailed analysis of the nonlinear characteristics of the modulator is conducted. Designed in IBM 130 nm 1.2 V CMOS technology and with a 100 kHz 100 mV input, the 1st order time-mode ΔΣ ADC exhibits an SNDR of 45.5 dB over 0.4 MHz bandwidth with power dissipation of 1.1mW. In comparison, the 2nd order ADC provides 54.8 dB SNDR, which equivalently offers an ENOB of 8.8 and it consumes 1.45 mW RMS power. The figure- of-merit of the 2nd order time-mode ΔΣ ADC is 407 pJ/step. Since the order of the system cannot be increased by simply cascading more differentiator stages, a time-mode ΔΣ ADC architecture employing a time-mode loop filter is suggested in the last chapter. Several key building blocks including a time amplifier, time register and time adder for implementing such a loop filter are presented. The time amplifier has an input dynamic range of 50ps and provides a gain of 20. The implemented time register has a dynamic range of 5ns and a peak error of 2% over the 5ns full scale. The time adder remains high accuracy as long as the input time difference is no greater than 1:6ns.

A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

2017 ◽  
Vol 26 (05) ◽  
pp. 1750073
Author(s):  
Abdullah El-Bayoumi ◽  
Hassan Mostafa ◽  
Ahmed M. Soliman
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Digital Converter ◽  
Pulse Delay ◽  
Fully Differential ◽  
Metal Insulator Metal ◽  
Simulation Results

Time-based Analog-to-Digital Converter (TADC), plays a major role in designing Software-Defined Radio (SDR) receivers, at scaled CMOS technologies, as it manifests lower area and power than conventional ADCs. TADC consists of 2 major blocks. The input voltage is converted into a pulse delay using a Voltage-to-Time Converter (VTC). In additions, the pulse delay is converted into a digital word using a Time-to-Digital Converter (TDC). In this paper, a novel fully-differential VTC based on a new methodology is presented which reports a highly-linear design. A metal-insulator-metal (MIM) capacitor as well as a dynamic calibration technique based on a set of large-sized capacitor-based voltage dividers circuits are utilized to automatically compensate the Process-Voltage-Temperature (PVT) variations. Moreover, the layout design is introduced. The proposed design operates on a 1[Formula: see text]GS/s sampling frequency with a supply voltage of 1.2[Formula: see text]V. After calibration, simulation results, using TSMC 65[Formula: see text]nm CMOS technology, report a 1.42[Formula: see text]V wider dynamic range due to the differential mechanism with a 3% linearity error. This design achieves a resolution up to 14 bits, a 0.07 fJ/conversion FOM, a 229[Formula: see text][Formula: see text]m2 area and a 0.25[Formula: see text]mW power. The simulation results are compared to the single-ended VTC results and the state-of-the-art analog-part ADCs results to show the strength of the proposed design.

scholarly journals Time-mode signal processing and application in ΔΣ ADC design

2021 ◽  
Author(s):  
Guangyu Zhu
Keyword(s):  
Dynamic Range ◽  
Building Blocks ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Noise Shaping ◽  
Loop Filter ◽  
Linear Effect ◽  
Circuit Components ◽  
Δσ Adc ◽  
Time Amplifier

An all-digitally implemented 1st order and a 2nd order time-mode ΔΣ ADCs are proposed and presented in this dissertation. Each proposed ΔΣ ADC consists of a voltage-to- time integration converter, a seven-stage gated ring oscillator functioning as a 3-bit quantizer, and a 7-stage digital differentiator that provides noise-shaping and frequency feedback. The 2nd order architecture differs from the 1st order by cascading two digital differentiators. The 2nd order design improves noise-shaping characteristic and SNDR. However it does not effectively suppress the harmonic tones due to the non-linear effect of the circuit components. Thus a detailed analysis of the nonlinear characteristics of the modulator is conducted. Designed in IBM 130 nm 1.2 V CMOS technology and with a 100 kHz 100 mV input, the 1st order time-mode ΔΣ ADC exhibits an SNDR of 45.5 dB over 0.4 MHz bandwidth with power dissipation of 1.1mW. In comparison, the 2nd order ADC provides 54.8 dB SNDR, which equivalently offers an ENOB of 8.8 and it consumes 1.45 mW RMS power. The figure- of-merit of the 2nd order time-mode ΔΣ ADC is 407 pJ/step. Since the order of the system cannot be increased by simply cascading more differentiator stages, a time-mode ΔΣ ADC architecture employing a time-mode loop filter is suggested in the last chapter. Several key building blocks including a time amplifier, time register and time adder for implementing such a loop filter are presented. The time amplifier has an input dynamic range of 50ps and provides a gain of 20. The implemented time register has a dynamic range of 5ns and a peak error of 2% over the 5ns full scale. The time adder remains high accuracy as long as the input time difference is no greater than 1:6ns.

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

2015 ◽  
Vol 24 (06) ◽  
pp. 1550093 ◽  
Author(s):  
Dengquan Li ◽  
Liang Zhang ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Single Channel ◽  
Mode Selection ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Timing Errors ◽  
Delay Locked Loop ◽  
Simulation Results ◽  
On Chip ◽  
Time Interleaved

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

scholarly journals Modeling of German Low Voltage Cables with Ground Return Path

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1265 ◽  
Author(s):  
Johanna Geis-Schroer ◽  
Sebastian Hubschneider ◽  
Lukas Held ◽  
Frederik Gielnik ◽  
Michael Armbruster ◽  
...  
Keyword(s):  
Low Voltage ◽  
Measurement Data ◽  
Analytical Calculation ◽  
Laboratory Measurement ◽  
Model Parameters ◽  
Calculation Methods ◽  
Modeling Approach ◽  
Measurement Results ◽  
Simulation Results ◽  
Return Path

In this contribution, measurement data of phase, neutral, and ground currents from real low voltage (LV) feeders in Germany is presented and analyzed. The data obtained is used to review and evaluate common modeling approaches for LV systems. An alternative modeling approach for detailed cable and ground modeling, which allows for the consideration of typical German LV earthing conditions and asymmetrical cable design, is proposed. Further, analytical calculation methods for model parameters are described and compared to laboratory measurement results of real LV cables. The models are then evaluated in terms of parameter sensitivity and parameter relevance, focusing on the influence of conventionally performed simplifications, such as neglecting house junction cables, shunt admittances, or temperature dependencies. By comparing measurement data from a real LV feeder to simulation results, the proposed modeling approach is validated.

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