An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

2015 ◽  
Vol 24 (06) ◽  
pp. 1550093 ◽  
Author(s):  
Dengquan Li ◽  
Liang Zhang ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Single Channel ◽  
Mode Selection ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Timing Errors ◽  
Delay Locked Loop ◽  
Simulation Results ◽  
On Chip ◽  
Time Interleaved

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

A POWER AND AREA EFFICIENT 65 nm CMOS DELAY-LINE ADC FOR ON-CHIP VOLTAGE SENSING

2013 ◽  
Vol 22 (09) ◽  
pp. 1340014 ◽  
Author(s):  
SIDA AMY SHEN ◽  
SHUANG XIE ◽  
WAI TUNG NG
Keyword(s):  
Power Management ◽  
Delay Line ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Voltage Sensing ◽  
Circuit Performance ◽  
Analog To Digital ◽  
Dynamic Voltage ◽  
On Chip ◽  
Area Efficient

This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC consumes 14 μW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

scholarly journals A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Yi Zhang ◽  
Qiao Meng ◽  
Changchun Zhang ◽  
Ying Zhang ◽  
Yufeng Guo ◽  
...  
Keyword(s):  
Single Channel ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Zero Crossing ◽  
Chip Area ◽  
Analog To Digital ◽  
Bootstrapped Switch ◽  
Foreground Calibration ◽  
Two Stages ◽  
Crossing Point

A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

scholarly journals 10-Bit, 1GS/S Time-Interleaved SAR ADC

2021 ◽  
Author(s):  
Shravan Kumar Donthula ◽  
Supravat Debnath
Keyword(s):  
Power Consumption ◽  
Single Channel ◽  
Search Algorithm ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Signal Frequency ◽  
Clock Frequency ◽  
Successive Approximation Adc ◽  
Time Interleaved

This paper describes the implementation of a 4-channel, 10-bit, 1 GS/s time-interleaved analog to digital converter (TI-ADC) in 65nm CMOS technology. Each channel consists of interleaved T/H and ADC array operating at 250 MS/s, with each ADC array containing 14 timeinterleaved sub-ADCs. This configuration provides high sampling rate even though each subADC works at a moderate sampling rate. We have selected 10-bit successive approximation ADC (SAR ADC) as a sub-ADC, since this architecture is most suitable for low power and medium resolution. SAR ADC works on binary search algorithm, since it resolves 1-bit at a time. The target sampling rate was 20 MS/s in this design, however the sampling rate achieved is 15 MS/s. As a result, the 10-bit SAR ADC operates at 15 MS/s with power consumption of 560 μW at 1.2 V supply and achieves SNDR of 57 dB (i.e. ENOB 9.2 bits) near nyquist rate input. The resulting Figure of Merit (FoM) is 63.5 fJ/step. The achieved DNL and INL is +0.85\-0.9 LSB and +1\-1.1 LSB respectively. The 10-bit SAR ADC occupies an active area of 300 μm × 440 μm. The functionality of single channel TI-SAR ADC has been verified by simulation with input signal frequency of 33.2 MHz and clock frequency of 250 MHz. The desired SNDR of 59.3 dB has been achieved with power consumption of 11.6 mW. This results in a FoM value of 60 fJ/step.

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS

2013 ◽  
Vol 433-435 ◽  
pp. 1463-1469 ◽  
Author(s):  
Yi Lin Zheng ◽  
Ying Mei Chen ◽  
Jian Wei Gong ◽  
Jian Guo Yao
Keyword(s):  
Laser Diode ◽  
Cmos Technology ◽  
Radio Over Fiber ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Linear Amplifier ◽  
Simulation Results ◽  
On Chip ◽  
Dynamic Bias

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 534 ◽  
pp. 197-205
Author(s):  
Kiichi Niitsu ◽  
Masato Sakurai ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Daiki Oki ◽  
...  
Keyword(s):  
Power Supply ◽  
Analytical Study ◽  
Cmos Technology ◽  
High Accuracy ◽  
Spice Simulation ◽  
Supply Noise ◽  
Noise Injection ◽  
Simulation Results ◽  
On Chip ◽  
Frequency Detector

This work presents the analytical study on jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to analyze and estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture.

scholarly journals A Statistic-Based Calibration Method for TIADC System

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Kuojun Yang ◽  
Shulin Tian ◽  
Peng Ye ◽  
Peng Zhang ◽  
Yuanjin Zheng
Keyword(s):  
Sampling Rate ◽  
Calibration Method ◽  
Wide Frequency Range ◽  
Accurate Estimation ◽  
Analog To Digital ◽  
Average Value ◽  
Gain Error ◽  
Sampling Points ◽  
Interleaved Adc ◽  
Time Interleaved

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

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