scholarly journals Brain-Inspired Hardware Solutions for Inference in Bayesian Networks

2021 ◽  
Vol 15 ◽  
Author(s):  
Leila Bagheriye ◽  
Johan Kwisthout
Keyword(s):  
Bayesian Networks ◽  
Analog Circuits ◽  
Hardware Implementation ◽  
Computing Systems ◽  
Stochastic Computing ◽  
Computing Paradigm ◽  
Mixed Signal Circuits ◽  
Hardware Implementations ◽  
Implementation Problems ◽  
Recent Attention

The implementation of inference (i.e., computing posterior probabilities) in Bayesian networks using a conventional computing paradigm turns out to be inefficient in terms of energy, time, and space, due to the substantial resources required by floating-point operations. A departure from conventional computing systems to make use of the high parallelism of Bayesian inference has attracted recent attention, particularly in the hardware implementation of Bayesian networks. These efforts lead to several implementations ranging from digital circuits, mixed-signal circuits, to analog circuits by leveraging new emerging nonvolatile devices. Several stochastic computing architectures using Bayesian stochastic variables have been proposed, from FPGA-like architectures to brain-inspired architectures such as crossbar arrays. This comprehensive review paper discusses different hardware implementations of Bayesian networks considering different devices, circuits, and architectures, as well as a more futuristic overview to solve existing hardware implementation problems.

scholarly journals Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Punyashloka Debashis ◽  
Vaibhav Ostwal ◽  
Rafatul Faria ◽  
Supriyo Datta ◽  
Joerg Appenzeller ◽  
...  
Keyword(s):  
Bayesian Networks ◽  
Bayesian Network ◽  
Large Scale ◽  
Hardware Implementation ◽  
Reducing Power ◽  
Perpendicular Magnetic Anisotropy ◽  
Building Blocks ◽  
Spintronic Devices ◽  
Network Building ◽  
Hardware Implementations

Abstract Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the stochastic variables in a Bayesian network that encode the probability of occurrence of the associated event. This work presents an experimental demonstration of a Bayesian network building block implemented with inherently stochastic spintronic devices based on the natural physics of nanomagnets. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.

scholarly journals Search for a substring of characters using the theory of non-deterministic finite automata and vector-character architecture

2020 ◽  
Vol 9 (3) ◽  
pp. 1238-1250
Author(s):  
Dmitry V. Pashchenko ◽  
Dmitry A. Trokoz ◽  
Alexey I. Martyshkin ◽  
Mihail P. Sinev ◽  
Boris L. Svistunov
Keyword(s):  
Computational Complexity ◽  
Hardware Implementation ◽  
Finite Automata ◽  
Target Line ◽  
Computing Systems ◽  
Deterministic Finite Automata ◽  
Low Level ◽  
Hardware Implementations ◽  
The Future

The paper proposed an algorithm which purpose is searching for a substring of characters in a string. Principle of its operation is based on the theory of non-deterministic finite automata and vector-character architecture. It is able to provide the linear computational complexity of searching for a substring depending on the length of the searched string measured in the number of operations with hyperdimensional vectors when repeatedly searching for different strings in a target line. None of the existing algorithms has such a low level of computational complexity. The disadvantages of the proposed algorithm are the fact that the existing hardware implementations of computing systems for performing operations with hyperdimensional vectors require a large number of machine instructions, which reduces the gain from this algorithm. Despite this, in the future, it is possible to create a hardware implementation that can ensure the execution of operations with hyperdimensional vectors in one cycle, which will allow the proposed algorithm to be applied in practice.

A General Framework of Algorithm-Based Fault Tolerance Technique for Computing Systems

2014 ◽  
pp. 1-21 ◽  
Author(s):  
Hodjatollah Hamidi
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
General Framework ◽  
Fault Tolerant ◽  
Convolutional Code ◽  
Numerical Algorithms ◽  
Convolutional Codes ◽  
Computing Systems ◽  
Specific Level ◽  
Computing Paradigm

The Algorithm-Based Fault Tolerance (ABFT) approach transforms a system that does not tolerate a specific type of faults, called the fault-intolerant system, to a system that provides a specific level of fault tolerance, namely recovery. The ABFT philosophy leads directly to a model from which error correction can be developed. By employing an ABFT scheme with effective convolutional code, the design allows high throughput as well as high fault coverage. The ABFT techniques that detect errors rely on the comparison of parity values computed in two ways. The parallel processing of input parity values produce output parity values comparable with parity values regenerated from the original processed outputs and can apply convolutional codes for the redundancy. This method is a new approach to concurrent error correction in fault-tolerant computing systems. This chapter proposes a novel computing paradigm to provide fault tolerance for numerical algorithms. The authors also present, implement, and evaluate early detection in ABFT.

scholarly journals Thermodynamic Computing: An Intellectual and Technological Frontier

Proceedings ◽  
2020 ◽  
Vol 47 (1) ◽  
pp. 23
Author(s):  
Todd Hylton
Keyword(s):  
Machine Learning ◽  
Device Fabrication ◽  
Power Supplies ◽  
Self Organization ◽  
Technological Systems ◽  
Computing Systems ◽  
Cooling Systems ◽  
Computing Paradigm ◽  
Transport Losses ◽  
State Changes

Concepts from thermodynamics are ubiquitous in computing systems today—e.g., in power supplies and cooling systems, in signal transport losses, in device fabrication, in state changes, and in the methods of machine learning. Here we propose that thermodynamics should be the central, unifying concept in future computing systems. In particular, we suppose that future computing technologies will thermodynamically evolve in response to electrical and information potential in their environment and, therefore, address the central challenges of energy efficiency and self-organization in technological systems. In this article, we summarize the motivation for a new computing paradigm grounded in thermodynamics and articulate a vision for such future systems.

A Low Power Hardware Implementation of Izhikevich Neuron using Stochastic Computing

2018 ◽  
Author(s):  
Aya A. Ismail ◽  
Zeinab A. Shaheen ◽  
Osama Rashad ◽  
Khaled N. Salama ◽  
Hassan Mostafa
Keyword(s):  
Low Power ◽  
Hardware Implementation ◽  
Stochastic Computing

scholarly journals Photoreduced nanocomposites of graphene oxide/N-doped carbon dots toward all-carbon memristive synapses

2020 ◽  
Vol 12 (1) ◽  
Author(s):  
Ya Lin ◽  
Zhongqiang Wang ◽  
Xue Zhang ◽  
Tao Zeng ◽  
Liang Bai ◽  
...  
Keyword(s):  
Pattern Recognition ◽  
Graphene Oxide ◽  
Hardware Implementation ◽  
High Accuracy ◽  
Computing Systems ◽  
Carbon Quantum Dot ◽  
Synaptic Functions ◽  
Local Reduction ◽  
Ultraviolet Light Irradiation ◽  
Doped Carbon Dots

Abstract An all-carbon memristive synapse is highly desirable for hardware implementation in future wearable neuromorphic computing systems. Graphene oxide (GO) can exhibit resistive switching (RS) and may be a feasible candidate to achieve this objective. However, the digital-type RS often occurring in GO-based memristors restricts the biorealistic emulation of synaptic functions. Here, an all-carbon memristive synapse with analog-type RS behavior was demonstrated through photoreduction of GO and N-doped carbon quantum dot (NCQD) nanocomposites. Ultraviolet light irradiation induced the local reduction of GO near the NCQDs, therefore forming multiple weak conductive filaments and demonstrating analog RS with a continuous conductance change. This analog RS enabled the close emulation of several essential synaptic plasticity behaviors; more importantly, the high linearity of the conductance change also facilitated the implementation of pattern recognition with high accuracy. Furthermore, the all-carbon memristive synapse can be transferred onto diverse substrates, showing good flexibility and 3D conformality. Memristive potentiation/depression was stably performed at 450 K, indicating the resistance of the synapse to high temperature. The photoreduction method provides a new path for the fabrication of all-carbon memristive synapses, which supports the development of wearable neuromorphic electronics.

scholarly journals Stochastic Computing for Hardware Implementation of Binarized Neural Networks

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 76394-76403 ◽  
Author(s):  
Tifenn Hirtzlin ◽  
Bogdan Penkovsky ◽  
Marc Bocquet ◽  
Jacques-Olivier Klein ◽  
Jean-Michel Portal ◽  
...  
Keyword(s):  
Neural Networks ◽  
Hardware Implementation ◽  
Stochastic Computing

Role-Based Autonomic Systems

2010 ◽  
Vol 2 (3) ◽  
pp. 32-51 ◽  
Author(s):  
Haibin Zhu
Keyword(s):  
Autonomic Computing ◽  
Self Management ◽  
Self Awareness ◽  
Self Healing ◽  
Systems Management ◽  
Computing Systems ◽  
Computing Paradigm ◽  
Role Based ◽  
Coordination And Collaboration ◽  
Self Protection

Autonomic Computing is an emerging computing paradigm used to create computer systems capable of self-management in order to overcome the rapidly growing complexity of computing systems management. To possess self-* properties, there must be mechanisms to support self-awareness, that is an autonomic system should be able to perceive the abnormality of its components. After abnormality is checked, processes of self-healing, self-configuration, self-optimization, and self-protection must be completed to guarantee the system works correctly and continuously. In role-based collaboration (RBC), roles are the major media for interaction, coordination, and collaboration. A role can be used to check if a player behaves well or not. This paper investigates the possibility of using roles and their related mechanisms to diagnose the behavior of agents, and facilitate self-* properties of a system.

RADIATION-TOLERANT DESIGN FOR HIGH PERFORMANCE MIXED-SIGNAL CIRCUITS

2004 ◽  
Vol 14 (02) ◽  
pp. 353-366 ◽  
Author(s):  
W. T. HOLMAN
Keyword(s):  
Integrated Circuits ◽  
Analog Circuits ◽  
High Performance ◽  
Radiation Effects ◽  
Mixed Signal ◽  
Mixed Signal Circuits ◽  
Dose Rate Effects ◽  
Current Design ◽  
Radiation Hardened ◽  
Radiation Tolerant

Modern semiconductor processes can provide significant intrinsic hardness against radiation effects in digital and analog circuits. Current design techniques using commercial processes for radiation-tolerant integrated circuits are summarized, with an emphasis on their application in high performance mixed-signal circuits and systems. Examples of "radiation hardened by design" (RHBD) methodologies are illustrated for reducing the vulnerability of circuits and components to total dose, single-event, and dose-rate effects.

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