A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

2014 ◽  
Vol 61 (5) ◽  
pp. 304-308 ◽  
Keyword(s):  
Cmos Process ◽  
On Chip ◽  
Output Driver

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hole Mobility ◽  
Micro Electro Mechanical System ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Ir Sensor ◽  
Cantilever Structure ◽  
Cmos Mems ◽  
On Chip ◽  
Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

scholarly journals A mm-Sized Free-Floating Wireless Implantable Opto-Electro Stimulation Device

Micromachines ◽  
2020 ◽  
Vol 11 (6) ◽  
pp. 621
Author(s):  
Yaoyao Jia ◽  
Yan Gong ◽  
Arthur Weber ◽  
Wen Li ◽  
Maysam Ghovanloo
Keyword(s):  
Electrical Stimulation ◽  
Large Scale ◽  
Electrode Array ◽  
Cmos Process ◽  
Optical Stimulation ◽  
In Vivo Experiments ◽  
Stimulation Mode ◽  
Shift Keying ◽  
On Chip

Towards a distributed neural interface, consisting of multiple miniaturized implants, for interfacing with large-scale neuronal ensembles over large brain areas, this paper presents a mm-sized free-floating wirelessly-powered implantable opto-electro stimulation (FF-WIOS2) device equipped with 16-ch optical and 4-ch electrical stimulation for reconfigurable neuromodulation. The FF-WIOS2 is wirelessly powered and controlled through a 3-coil inductive link at 60 MHz. The FF-WIOS2 receives stimulation parameters via on-off keying (OOK) while sending its rectified voltage information to an external headstage for closed-loop power control (CLPC) via load-shift-keying (LSK). The FF-WIOS2 system-on-chip (SoC), fabricated in a 0.35-µm standard CMOS process, employs switched-capacitor-based stimulation (SCS) architecture to provide large instantaneous current needed for surpassing the optical stimulation threshold. The SCS charger charges an off-chip capacitor up to 5 V at 37% efficiency. At the onset of stimulation, the capacitor delivers charge with peak current in 1.7–12 mA range to a micro-LED (µLED) array for optical stimulation or 100–700 μA range to a micro-electrode array (MEA) for biphasic electrical stimulation. Active and passive charge balancing circuits are activated in electrical stimulation mode to ensure stimulation safety. In vivo experiments conducted on three anesthetized rats verified the efficacy of the two stimulation mechanisms. The proposed FF-WIOS2 is potentially a reconfigurable tool for performing untethered neuromodulation.

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