scholarly journals A Self-Test, Self-Calibration and Self-Repair Methodology of Thermopile Infrared Detector

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1167
Author(s):  
Kaiyue Zhou ◽  
Jia Li ◽  
Weibing Wang ◽  
Dapeng Chen

To improve the reliability and yield of thermopile infrared detectors, a self-test, self-calibration and self-repair methodology is proposed in this paper. A novel micro-electro-mechanical system (MEMS) infrared thermopile detector structure is designed in this method with a heating resistor building on the center of the membrane. The heating resistor is used as the stimuli of the sensing element on chip to achieve a self-test, and the responsivity related with ambient temperature can be calibrated by the equivalent model between electrical stimuli and physical stimuli. Furthermore, a fault tolerance mechanism is also proposed to localize the fault and repair the detector if the detector fails the test. The simulation results with faults simulated by the Monte Carlo stochastic model show that the proposed scheme is an effective solution to improve the yield of the MEMS thermopile infrared detector.

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.


2016 ◽  
Vol 70 (5) ◽  
pp. 897-904 ◽  
Author(s):  
Mazen Erfan ◽  
Yasser M Sabry ◽  
Mohammad Sakr ◽  
Bassem Mortada ◽  
Mostafa Medhat ◽  
...  

2007 ◽  
Vol 7 (9) ◽  
pp. 1225-1232 ◽  
Author(s):  
Andrew Mason ◽  
Abhijeet V. Chavan ◽  
Kensall D. Wise

2011 ◽  
Vol 46 (9) ◽  
pp. 2041-2052 ◽  
Author(s):  
Jae-sun Seo ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  

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