scholarly journals HAL-ASOS Accelerator Model: Evolutive Elasticity by Design

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2078
Author(s):  
Vítor Silva ◽  
Paulo Pinto ◽  
Paulo Cardoso ◽  
Jorge Cabral ◽  
Adriano Tavares
Keyword(s):  
File System ◽  
Control Unit ◽  
Computing Unit ◽  
System Calls ◽  
Hardware System ◽  
Software Reconfiguration ◽  
Field Programmable ◽  
Significant Performance ◽  
Programmable Gate Arrays ◽  
Virtual File System

To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies.

scholarly journals Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System

2017 ◽  
Vol 25 (0) ◽  
pp. 42-48 ◽  
Author(s):  
Abul Hasnat ◽  
Anindya Ghosh ◽  
Amina Khatun ◽  
Santanu Halder
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Probabilistic Neural Network ◽  
Clock Period ◽  
Data Set ◽  
Gate Arrays ◽  
Hardware System ◽  
Field Programmable ◽  
Programmable Gate Arrays

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

scholarly journals Comparison of reconfigurable structures for flexible word-length multiplication

2008 ◽  
Vol 6 ◽  
pp. 113-118 ◽  
Author(s):  
O. A. Pfänder ◽  
R. Nopper ◽  
H.-J. Pfleiderer ◽  
S. Zhou ◽  
A. Bermak
Keyword(s):  
Power Dissipation ◽  
Word Length ◽  
Digital Signal ◽  
Gate Arrays ◽  
Computing Unit ◽  
Field Programmable ◽  
Embedded Blocks ◽  
Programmable Gate Arrays ◽  
Array Structures ◽  
Reconfigurable Structures

Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

Design of EMB-Based Moore FSMs

2017 ◽  
Vol 26 (07) ◽  
pp. 1750125 ◽  
Author(s):  
Małgorzata Kołopieńczyk ◽  
Larysa Titarenko ◽  
Alexander Barkalov
Keyword(s):  
Control Unit ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Complexity Of Algorithms ◽  
Gate Arrays ◽  
Control Units ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

scholarly journals Reconfigurable, Multi-channel and Modular Bioimpedance Spectroscopy System on Field Programmable Gate Arrays

2017 ◽  
Author(s):  
Anis Nurashikin Nordin ◽  
Ahmed Al-Hashimi ◽  
Amelia Wong Azman
Keyword(s):  
Flash Memory ◽  
Control Unit ◽  
Field Programmable Gate Arrays ◽  
Device Under Test ◽  
Gate Arrays ◽  
Final Data ◽  
Balance Bridge ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Spectroscopy System

This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.

scholarly journals Design of a Reconfigurable, Modular and Multi-Channel Bioimpedance Spectroscopy System

2017 ◽  
Vol 8 (2) ◽  
pp. 428
Author(s):  
Ahmed Al-Hashimi ◽  
Anis Nurashikin Nordin ◽  
Amelia Wong Azman
Keyword(s):  
Flash Memory ◽  
Control Unit ◽  
Device Under Test ◽  
Final Data ◽  
Balance Bridge ◽  
Field Programmable ◽  
Comparable Performance ◽  
Programmable Gate Arrays ◽  
Spectroscopy System ◽  
Processing And Storage

This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.

Research on File System Event Monitoring in Android Platform

2013 ◽  
Vol 443 ◽  
pp. 494-498 ◽  
Author(s):  
Rui Xia Zhang ◽  
Ya Liang Wang ◽  
Yan Lan Liu
Keyword(s):  
File System ◽  
Smart Phone ◽  
System Call ◽  
Event Monitoring ◽  
System Calls ◽  
Comprehensive Method ◽  
Android Platform ◽  
Significant Performance ◽  
Performance Gains ◽  
Android Api

Android is a standard and popular platform of various smart phone. Security thread is a major problem to smart phone. File system event monitoring is essential for many types of programs ranging from file managers to security tools. In this paper, we make research on file system event monitoring. Our approach involves file nodes monitor by Android API and Linux native system call. We compare different features between them. It shows that each method has its benefit and limitation. Linux system calls method outperforms API in flexibility and scalability. But it has its un-convenience to user for its page alignment. A comprehensive method is proposed to take advantage of significant performance gains.

Engineering Technology and Accounting Science: Evolution and Futures Agenda

2021 ◽  
Vol 9 (3) ◽  
pp. 227-230
Keyword(s):  
Information Technology ◽  
Educational Institutions ◽  
Conceptual Approach ◽  
Engineering Technology ◽  
Gate Arrays ◽  
Hardware System ◽  
5G Network ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Function

This paper makes a novel inroad into engineering technology influence on modern accounting science and therefore provides awareness to accounting and finance professionals, the corporate and educational institutions on how engineering technology has become inextricably intertwined with the practice and learning of accounting. The paper thus aims to highlight how engineering technology has influenced and is rechanneling accounting mode of operations and function through the advancement in information technology apparatus. Using a conceptual approach, it shows how accounting has become synonymous with engineering technology and as such triggers the impetus for revamping accounting curriculum to accommodate the fundamental aspects of engineering study before concentrating on the core accounting modules. Accordingly, the paper makes initial recommendation for some information technology (IT)modules to form part of future accounting engineering curriculum. The IT modules that are proposed includes inter alia, cloud accounting, 5G Network and IOT Hardware System, Field-programmable gate arrays (FPGA), 3-D circuit architecture, Internet of Things and Industry 4.0, understanding and operation of Context-Aware Engine (CAE).

A DSP–FPGA-BASED RECONFIGURABLE COMPUTER

1998 ◽  
Vol 08 (04) ◽  
pp. 453-459
Author(s):  
G. K. ROSENDAHL ◽  
R. D. MCLEOD ◽  
H. C. CARD
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Parallel Machine ◽  
Post Processing ◽  
Communication Performance ◽  
Gate Arrays ◽  
Broadcast Network ◽  
Software Reconfiguration ◽  
Field Programmable ◽  
Programmable Gate Arrays

In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs. The system has been successfully tested on several applications in signal processing.

scholarly journals FPGA Fast Simulation of Tsunami Wave Propagation

2021 ◽  
pp. 14-25
Author(s):  
М. М. Лаврентьев ◽  
К. Ф. Лысаков ◽  
А. Г. Марчук ◽  
К. К. Облаухов
Keyword(s):  
Wave Propagation ◽  
Shallow Water ◽  
Tsunami Wave ◽  
Quantitative Estimation ◽  
Kamchatka Peninsula ◽  
Modern Computer ◽  
The Pacific ◽  
Field Programmable ◽  
Significant Performance ◽  
Programmable Gate Arrays

В данной статье рассматривается решение задачи быстрой численной оценки высоты волн цунами от гипотетического очага вдоль тихоокеанского побережья полуострова Камчатка и Курильских островов. Мы фокусируемся на очень быстром (практически в режиме поступления данных) численном моделировании распространения волны цунами на основе ПК в соответствии с классическим приближением теории мелкой воды. Существенный прирост производительности достигается за счет использования преимуществ современных компьютерных архитектур, а именно вентильных матриц, программируемых пользователем (Field Programmable Gate Array – FPGA). Разностная схема Мак-Кормака второго порядка аппроксимации для решения системы дифференциальных уравнений мелкой воды [1] реализована на чипе FPGA в составе платы, специально разработанной авторами для решения этой задачи [2, 3]. Численные тесты показывают, что для расчета 3600 шагов по времени распространения волны цунами в расчетной области размером приблизительно 2000х2000 км (3120х2400 расчетных узлов) требуется всего несколько секунд для моделирования цунами от модельного источника волны цунами на сетке с пространственным шагом около 900 м. Созданный на базе FPGA спецвычислитель был также протестирован по точности сравнением с аналитическими решениями, полученными Ан. Марчуком [4, 5] для некоторых модельных топографий дна. The study offers a fast quantitative estimation of tsunami wave heights coming from a hypothetical source along the Pacific coast of the Kamchatka Peninsula and the Kuril Islands. We focus on a very fast (virtually real-time) PC simulation of tsunami wave propagation using the classical approximation of the shallow water theory. Significant performance gains are achieved by taking advantage of modern computer architectures, namely Field Programmable Gate Arrays (FPGAs). The McCormack difference scheme of the second order of approximation for solving the system of shallow water differential equations [1] is implemented with an FPGA chip on a custom PCB designed by the authors [2, 3]. Numerical tests indicate that it takes only a few seconds to simulate a tsunami wave from a simulated source on a 900 m spacing grid to analyze 3,600 time increments of propagation of the tsunami wave propagation in about 2000x2000 km area (3,120x2,400 nodes.) The customized FPGA computer was also tested for accuracy by comparing with the analytical solutions obtained by Marchuk [4, 5] for some reference bottom topographies.  

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