scholarly journals Per-Core Power Modeling for Heterogenous SoCs

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2428
Author(s):  
Ganapati Bhat ◽  
Sumit K. Mandal ◽  
Sai T. Manchukonda ◽  
Sai V. Vadlamudi ◽  
Ayushi Agarwal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Graphics Processing Units ◽  
Total Power ◽  
Power Modeling ◽  
Mobile Platforms ◽  
Multiple Resources ◽  
Wide Range ◽  
Total Power Consumption ◽  
On Chip ◽  
The One

State-of-the-art mobile platforms, such as smartphones and tablets, are powered by heterogeneous system-on-chips (SoCs). These SoCs are composed of many processing elements, including multiple CPU core clusters (e.g., big.LITTLE cores), graphics processing units (GPUs), memory controllers and other on-chip resources. On the one hand, mobile platforms need to provide a swift response time for interactive apps and high throughput for graphics-oriented workloads; on the other hand, the power consumption must be under tight control to prevent high skin temperatures and energy consumption. Therefore, commercial systems feature a range of mechanisms for dynamic power and temperature control. However, these techniques rely on simple indicators, such as core utilization and total power consumption. System architects are typically limited to the total power consumption, since multiple resources share the same power rail. More importantly, most of the power rails are not exposed to the input/output pins. To address this challenge, this paper presents a thorough methodology to model the power consumption of major resources in heterogeneous SoCs. The proposed models utilize a wide range of performance counters to capture the workload dynamics accurately. Experimental validation on a Nexus 6P phone, powered by an octa-core Snapdragon 810 SoC, showed that the proposed models can estimate the power consumption within a 10% error margin.

Stable Matching based Virtual Channels Allocation Scheme in Network-on-Chip

2020 ◽  
Vol 20 (02) ◽  
pp. 2050008
Author(s):  
BANSIDHAR JOSHI ◽  
MANISH K. THAKUR
Keyword(s):  
Power Consumption ◽  
Network On Chip ◽  
Total Power ◽  
Allocation Scheme ◽  
Trade Off ◽  
Routing Schemes ◽  
Virtual Channels ◽  
Total Power Consumption ◽  
On Chip ◽  
The One

While designing router micro-architecture of an On-Chip network, a good allocation of virtual channels (VCs) governs an effective resources utilization which essentially results in an optimized number of packets received at destination(s). Generally, the VC allocation schemes deal with the one-way approach of VC allocation to the contending flits. However, this approach produces non-optimal matching of flits to the available VCs on next routers, and therefore leads to the under-utilization of these VCs. This paper proposes a 2-Way VC Allocation scheme to map input VCs (requestors) to output VCs (resources). The proposed scheme is compared with the conventional VC allocation scheme under two different mesh configurations with a 100% channel load. Simulations performed under two different routing schemes in diverse traffic scenarios demonstrate an increase in the number of packets received at destinations by up to 76%. Also, the network’s latency exhibits trade-off with total power consumption while reducing hotspots.

A SAT-Based Methodology for Effective Clock Gating for Power Minimization

2018 ◽  
Vol 28 (01) ◽  
pp. 1950011
Author(s):  
Khushbu Chandrakar ◽  
Suchismita Roy
Keyword(s):  
Power Consumption ◽  
Optimization Techniques ◽  
Total Power ◽  
Clock Signal ◽  
Clock Gating ◽  
Clock Tree ◽  
Synchronous Circuits ◽  
Design And Optimization ◽  
Total Power Consumption ◽  
On Chip

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to raise the level of abstraction for the design and optimization. A better optimization of performance and power can be achieved at higher abstraction levels by applying suitable optimization techniques. Insertion of clock gating logic into the generated Register-Transfer Level (RTL) would facilitate lowering dynamic power consumption by switching off the clock signal to portions of the circuit not currently in use and thereby reducing unnecessary toggling. In this work, we have tried to minimize the power consumption of synchronous circuits by reducing the number of activity string patterns. Activity-driven clock trees have been used wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies additional control signals and gates, there is always a trade-off existing between the logic circuit area overhead and the total power consumption of the clock tree. A pseudo-Boolean satisfiability (PB-SAT)-based approach is proposed in this work which focuses on the reduction of power consumption by reducing the activity pattern of the clock tree which will reduce the power consumption with appropriate module-binding solutions.

scholarly journals Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

2018 ◽  
Vol 10 (2) ◽  
pp. 514
Author(s):  
Ng Yen Phing ◽  
M.N. Mohd Warip ◽  
Phaklen Ehkan ◽  
S.Y. Teo
Keyword(s):  
Power Consumption ◽  
Large Scale ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Total Power ◽  
Clustering Method ◽  
Mesh Topology ◽  
Total Power Consumption ◽  
Promising Solution ◽  
On Chip

<span lang="EN-US">Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.</span>

scholarly journals Phase-Based Accurate Power Modeling for Mobile Application Processors

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1197
Author(s):  
Kitak Lee ◽  
Seung-Ryeol Ohk ◽  
Seong-Geun Lim ◽  
Young-Jin Kim
Keyword(s):  
Power Consumption ◽  
Mobile Application ◽  
Total Power ◽  
Average Error ◽  
Power Model ◽  
Power Modeling ◽  
Estimation Errors ◽  
Total Power Consumption ◽  
Battery Capacity ◽  
Power Models

Modern mobile application processors are required to execute heavier workloads while the battery capacity is rarely increased. This trend leads to the need for a power model that can analyze the power consumed by CPU and GPU at run-time, which are the key components of the application processor in terms of power savings. We propose novel CPU and GPU power models based on the phases using performance monitoring counters for smartphones. Our phase-based power models employ combined per-phase power modeling methods to achieve more accurate power consumption estimations, unlike existing power models. The proposed CPU power model shows estimation errors of 2.51% for ARM Cortex A-53 and 1.97% for Samsung M1 on average, and the proposed GPU power model shows an average error of 8.92% for the Mali-T880. In addition, we integrate proposed CPU and GPU models with the latest display power model into a holistic power model. Our holistic power model can estimate the smartphone′s total power consumption with an error of 6.36% on average while running nine 3D game benchmarks, improving the error rate by about 56% compared with the latest prior model.

scholarly journals Efficient Operation Method of Aquifer Thermal Energy Storage System Using Demand Response

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3129
Author(s):  
Jewon Oh ◽  
Daisuke Sumiyoshi ◽  
Masatoshi Nishioka ◽  
Hyunbae Kim
Keyword(s):  
Energy Storage ◽  
Power Consumption ◽  
Thermal Energy ◽  
Demand Response ◽  
Thermal Energy Storage ◽  
Heat Storage ◽  
Storage System ◽  
Total Power ◽  
Operation Method ◽  
Total Power Consumption

The mass introduction of renewable energy is essential to reduce carbon dioxide emissions. We examined an operation method that combines the surplus energy of photovoltaic power generation using demand response (DR), which recognizes the balance between power supply and demand, with an aquifer heat storage system. In the case that predicts the occurrence of DR and performs DR storage and heat dissipation operation, the result was an operation that can suppress daytime power consumption without increasing total power consumption. Case 1-2, which performs nighttime heat storage operation for about 6 h, has become an operation that suppresses daytime power consumption by more than 60%. Furthermore, the increase in total power consumption was suppressed by combining DR heat storage operation. The long night heat storage operation did not use up the heat storage amount. Therefore, it is recommended to the heat storage operation at night as much as possible before DR occurs. In the target area of this study, the underground temperature was 19.1 °C, the room temperature during cooling was about 25 °C and groundwater could be used as the heat source. The aquifer thermal energy storage (ATES) system in this study uses three wells, and consists of a well that pumps groundwater, a heat storage well that stores heat and a well that used heat and then returns it. Care must be taken using such an operation method depending on the layer configuration.

scholarly journals A Novel Differential Log-Companding Amplifier for Biosignal Sensing

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Zigang Dong ◽  
Xiaolin Zhou ◽  
Yuanting Zhang
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
New Method ◽  
Total Power ◽  
Maximum Output ◽  
Output Current ◽  
Current Range ◽  
Symmetrical Configuration ◽  
Total Power Consumption

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

Exergy Analysis of a Novel Cryogenic Concept for the Liquefaction of Natural Gas Integrated Into an Air Separation Process

2016 ◽  
Author(s):  
S. Tesch ◽  
T. Morosuk ◽  
G. Tsatsaronis
Keyword(s):  
Natural Gas ◽  
Power Consumption ◽  
Exergy Analysis ◽  
Primary Energy ◽  
Separation Process ◽  
Air Separation ◽  
Total Power ◽  
Separation Unit ◽  
Total Power Consumption ◽  
Liquefaction Temperature

The increasing demand for primary energy leads to a growing market of natural gas and the associated market for liquefied natural gas (LNG) increases, too. The liquefaction of natural gas is an energy- and cost-intensive process. After exploration, natural gas, is pretreated and cooled to the liquefaction temperature of around −160°C. In this paper, a novel concept for the integration of the liquefaction of natural gas into an air separation process is introduced. The system is evaluated from the energetic and exergetic points of view. Additionally, an advanced exergy analysis is conducted. The analysis of the concepts shows the effect of important parameters regarding the maximum amount of liquefiable of natural gas and the total power consumption. Comparing the different cases, the amount of LNG production could be increased by two thirds, while the power consumption is doubled. The results of the exergy analysis show, that the introduction of the liquefaction of natural gas has a positive effect on the exergetic efficiency of a convetional air separation unit, which increases from 38% to 49%.

scholarly journals Low-Threshold, High-Power On-Chip Tunable III-V/Si Lasers with Integrated Semiconductor Optical Amplifiers

2021 ◽  
Vol 11 (23) ◽  
pp. 11096
Author(s):  
Joan Manel Ramírez ◽  
Pierre Fanneau de la Horie ◽  
Jean-Guy Provost ◽  
Stéphane Malhouitre ◽  
Delphine Néel ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Optical Networks ◽  
Optical Amplifiers ◽  
Semiconductor Optical Amplifiers ◽  
Optical Amplifier ◽  
Silicon On Insulator ◽  
Total Power ◽  
Multiple Quantum ◽  
Total Power Consumption ◽  
On Chip

Heterogeneously integrated III-V/Si lasers and semiconductor optical amplifiers (SOAs) are key devices for integrated photonics applications requiring miniaturized on-chip light sources, such as in optical communications, sensing, or spectroscopy. In this work, we present a widely tunable laser co-integrated with a semiconductor optical amplifier in a heterogeneous platform that combines AlGaInAs multiple quantum wells (MQWs) and InP-based materials with silicon-on-insulator (SOI) wafers containing photonic integrated circuits. The co-integrated device is compact, has a total device footprint of 0.5 mm2, a lasing current threshold of 10 mA, a selectable wavelength tuning range of 50 nm centered at λ = 1549 nm, a fiber-coupled output power of 10 mW, and a laser linewidth of ν = 259 KHz. The SOA provides an on-chip gain of 18 dB/mm. The total power consumption of the co-integrated devices remains below 0.5 W even for the most power demanding lasing wavelengths. Apart from the above-mentioned applications, the co-integration of compact widely tunable III-V/Si lasers with on-chip SOAs provides a step forward towards the development of highly efficient, portable, and low power systems for wavelength division multiplexed passive optical networks (WDM-PONs).

scholarly journals Optimization of Power Consumption for the Design of 802.11n MIMO_OFDM System

2018 ◽  
Vol 26 (4) ◽  
pp. 172-184
Author(s):  
Muthna Jasim Fadhil
Keyword(s):  
Power Consumption ◽  
Orthogonal Frequency Division Multiplexing ◽  
High Speed ◽  
Mimo Systems ◽  
Total Power ◽  
Wireless System ◽  
Generator System ◽  
Total Power Consumption ◽  
Consumption Energy ◽  
High Reduction

In modern systems communication, different methods have been improved to change the prior imitative techniques that process communication data with high speed. It is necessary to improve (OFDM) Orthogonal Frequency Division Multiplexing technique because the development in the guideline communication of wireless system which include security data and transmission data reliability. The applications communications of wireless is important to develop in order to optimize the process of communication leads to reduce the level consumption energy of the output level signal. The architecture of VLSI is used to optimize the performance transceiver in 802.11 n OFDM-MIMO systems, this idea concentrate on the design of 6x6 MIMO_OFDM system in software simulink of MATLAB then using generator system for transfer to code of VHDL and applying in FPGA Xilinx Spartan 3 XC3S200 . The modelsim used to get the simulation while Xilinx power estimator is used to calculate power. The results registered total power consumption about 94mW while compared with previous work  was 136mW which means a high reduction of about 30.8% .

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