scholarly journals Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 325 ◽  
Author(s):  
Srinath Balasubramanian ◽  
Arunapriya Panchanathan ◽  
Bharatiraja Chokkalingam ◽  
Sanjeevikumar Padmanaban ◽  
Zbigniew Leonowicz
Keyword(s):  
Integrated Circuits ◽  
Supply Voltage ◽  
State Of The Art ◽  
Power Reduction ◽  
Significant Rise ◽  
Tree Representation ◽  
Voltage Level ◽  
Island Constraints ◽  
Functional Blocks ◽  
Representation Scheme

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

scholarly journals An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2795
Author(s):  
B. Srinath ◽  
Rajesh Verma ◽  
Abdulwasa Bakr Barnawi ◽  
Ramkumar Raja ◽  
Mohammed Abdul Muqeet ◽  
...  
Keyword(s):  
Simulated Annealing ◽  
Integrated Circuits ◽  
Supply Voltage ◽  
Physical Design ◽  
Timing Constraints ◽  
Clock Distribution ◽  
Clock Skew ◽  
Tree Representation ◽  
Optimization Parameters ◽  
Simulation Results

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

Dependence of Current Harmonics of Greenhouse Irradiators on Supply Voltage

2020 ◽  
pp. 85-88 ◽  
Author(s):  
Nadezhda P. Kondratieva
Keyword(s):  
Mathematical Models ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Feasibility Studies ◽  
Power Losses ◽  
Voltage Level ◽  
Supply Networks ◽  
Current Harmonics ◽  
Cable Lines ◽  
Harmonic Composition

The article describes the results of the study concerning the effect of the voltage level on current harmonic composition in greenhouses irradiators. It is found that its change affects the level of current harmonics of all types of the studied greenhouse irradiators. With decrease of nominal supply voltage by 10 %, the total harmonic distortion THDi decreases by 9 % for emitters equipped with high pressure sodium lamps (HPSL), by 10 % for emitters with electrode-less lamps and by 3 % for LED based emitters. With increase of nominal supply voltage by 10 %, THDi increases by 23 % for lighting devices equipped with HPSL, by 10 % for irradiators with electrode-less lamps and by 3 % for LED based emitters. Therefore, changes of supply voltage cause the least effect on the level of current harmonics of LED based emitters and then the emitters with electrode-less lamps. Change of the level of supply voltage causes the greatest effect on the level of current harmonics of HPSL based irradiators. Mathematical models of dependence of THDi on the level of supply voltage for greenhouse emitters equipped with LED, electrode-less lamps and HPSL lamps were formulated. These mathematical models may be used for calculations of total current when selecting transformers and supply cable lines for greenhouse lighting devices, for design of new or reconstruction of existing irradiation systems of greenhouse facilities, and for calculation of power losses in power supply networks of greenhouse facilities during feasibility studies for energy saving and energy efficiency increasing projects.

Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits

2013 ◽  
Vol E96.C (4) ◽  
pp. 538-545
Author(s):  
Takeshi OKUMOTO ◽  
Kumpei YOSHIKAWA ◽  
Makoto NAGATA
Keyword(s):  
Integrated Circuits ◽  
Supply Voltage

Passive Components for RF-ICs

2012 ◽  
pp. 189-214
Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez
Keyword(s):  
Integrated Circuits ◽  
Quality Factor ◽  
Silicon Substrate ◽  
Supply Voltage ◽  
Magnetic Behavior ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Fully Integrated ◽  
Core Elements ◽  
Low Supply Voltage

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.

Layer Optimization for Power Reduction in Integrated Circuits

2018 ◽  
Author(s):  
Lekbir Cherif ◽  
Mohamed Chentouf ◽  
Jalal Benallal ◽  
Mohammed Darmi ◽  
Rachid Elgouri ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Reduction

scholarly journals Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 611 ◽  
Author(s):  
Ik Joon Chang ◽  
Yesung Kang ◽  
Youngmin Kim
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Channel Length ◽  
Voltage Level ◽  
Exact Data ◽  
Optimum Energy ◽  
The Stability ◽  
20 Nm ◽  
Near Threshold

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

64 Channel ASIC for Neurobiology Experiments

2010 ◽  
Vol 56 (4) ◽  
pp. 375-380 ◽  
Author(s):  
Paweł Gryboś ◽  
Piotr Kmon ◽  
Robert Szczygieł ◽  
Mirosław Żołądź
Keyword(s):  
Integrated Circuits ◽  
Single Channel ◽  
Supply Voltage ◽  
Single Output ◽  
Application Specific Integrated Circuits ◽  
Coupling Circuit ◽  
Analogue Signals ◽  
Readout Channel ◽  
Application Specific

64 Channel ASIC for Neurobiology ExperimentsThis paper presents the design and measurements of 64 channel Application Specific Integrated Circuits (ASIC) for recording signals in neurobiology experiments. The ASIC is designed in 180 nm technology and operates with ± 0.9 V supply voltage. Single readout channel is built of AC coupling circuit at the input and two amplifier stages. In order to reduce the number of output lines, the 64 analogue signals from readout channels are multiplexed to a single output by an analogue multiplexer. The gain of the single channel can be set either to 350 V/V or 700 V/V. The low and the high cut-off frequencies can be tuned in 9 ÷ 90 Hz and in the 1.6 ÷ 24 kHz range respectively. The input referred noise is 7 μV rms in the bandwidth 90 Hz - 1.6 kHz and 9 μV rms in the bandwidth 9 Hz - 24 kHz. The single channel consumes 200 μW of power and this together with other parameters make the chip suitable for recording neurobiology signals.

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