A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

In this paper, the influence of the DC-blocking capacitors leveraged in coplanar waveguide (CPW) matching networks is studied. CPW matching networks with series-connected DC-blocking capacitors are less sensitive to capacitance and are adopted in a 28 GHz power amplifier (PA). The PA targeting fifth-generation (5G) phased array is developed in 90 nm silicon-on-insulator complementary-metal-oxide-semiconductor (SOI CMOS) technology. A stacked field-effect-transistor (FET) architecture is elected in the output stage to boost the output power and reduce the die area. The PA with a core area of 0.31 mm2 demonstrates a maximum small signal gain of 13.7 dB and a −3 dB bandwidth of 6.3 GHz (22.9–29.2 GHz). The PA achieves a measured saturated output power (Psat) of 14.4 dBm and a peak power added efficiency (PAE) of 25% for continuous wave signals. At 24/25.6/28 GHz, the PA achieves +7.87/+9.16/+10.7 dBm measured output power and 6.21%/8.11%/10.17% PAE at −25 dBc error vector magnitude(EVM) for a 250 MHz-wide 64-quadrature amplitude modulation (64-QAM). The developed linear PA provides a great potential for low-cost 5G phased array transceivers.

Download Full-text

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

Applied Sciences ◽

10.3390/app11156708 ◽

2021 ◽

Vol 11 (15) ◽

pp. 6708

Author(s):

Janne P. Aikio ◽

Alok Sethi ◽

Mikko Hietanen ◽

Jere Rusanen ◽

Timo Rahkonen ◽

...

Keyword(s):

Power Amplifier ◽

Complementary Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Error Vector Magnitude ◽

Fully Integrated ◽

Power Added Efficiency ◽

Wireless Applications ◽

Ofdm Signal ◽

New Radio

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

Download Full-text

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

Circuit World ◽

10.1108/cw-08-2020-0209 ◽

2021 ◽

Vol ahead-of-print (ahead-of-print) ◽

Author(s):

Selvakumar Mariappan ◽

Jagadheswaran Rajendran ◽

Norlaili Mohd Noh ◽

Yusman Yusof ◽

Narendra Kumar

Keyword(s):

Output Power ◽

Power Amplifier ◽

Continuous Wave ◽

Complementary Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Third Order ◽

Content Type ◽

Power Added Efficiency ◽

Driver Amplifier ◽

Continuous Wave Signal

Purpose The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE). Design/methodology/approach The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity. Findings For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc. Originality/value In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Download Full-text

RF-MEMS multi-mode-matching networks for GaN power transistors

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078714000427 ◽

2014 ◽

Vol 6 (5) ◽

pp. 447-458 ◽

Cited By ~ 3

Author(s):

Sascha A. Figur ◽

Friedbert van Raay ◽

Rüdiger Quay ◽

Larissa Vietzorreck ◽

Volker Ziegler

Keyword(s):

Output Power ◽

Power Amplifier ◽

Rf Mems ◽

Operation Mode ◽

Maximum Output Power ◽

Maximum Output ◽

Mode Matching ◽

Power Added Efficiency ◽

Matching Networks ◽

Multi Mode

This work presents radio-frequency-microelectromechanical-system (RF-MEMS)-based tunable input- and output-matching networks for a multi-band gallium nitride (GaN) power-amplifier applications. In the first part, circuit designs are shown and characterized for a fixed operation mode of the transistor, i.e. either a maximum-output-power- or a maximum-power-added-efficiency (PAE)-mode, which are finally combined into a multi-mode-matching network (M3N); the M3N allows to tune the operation mode of the transistor independently of its operational frequency. The matching networks are designed to provide optimum matching for the power amplifier at three to six different operating frequencies for maximum-output-power- and maximum-PAE-mode. In the frequency range from 3.5 to 8.5 GHz, return losses of 10 dB and higher were measured and insertion losses of 0.5–1.9 dB were demonstrated for the output-matching networks. Further characterizations were performed to test the dependency on the RF-input power, and no changes were observed up to power levels of 34 dBm when cold-switched.

Download Full-text

A highly efficient 3.5 GHz inverse class-F GaN HEMT power amplifier

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078710000395 ◽

2010 ◽

Vol 2 (3-4) ◽

pp. 317-324 ◽

Cited By ~ 8

Author(s):

Paul Saad ◽

Christian Fager ◽

Hossein Mashad Nemati ◽

Haiying Cao ◽

Herbert Zirath ◽

...

Keyword(s):

Output Power ◽

Power Amplifier ◽

Continuous Wave ◽

High Electron Mobility Transistor ◽

High Electron ◽

Power Added Efficiency ◽

Average Ratio ◽

Gan Hemt ◽

Continuous Wave Signal ◽

Class F

This paper presents the design and implementation of an inverse class-F power amplifier (PA) using a high power gallium nitride high electron mobility transistor (GaN HEMT). For a 3.5 GHz continuous wave signal, the measurement results show state-of-the-art power-added efficiency (PAE) of 78%, a drain efficiency of 82%, a gain of 12 dB, and an output power of 12 W. Moreover, over a 300 MHz bandwidth, the PAE and output power are maintained at 60% and 10 W, respectively. Linearized modulated measurements using 20 MHz bandwidth long-term evolution (LTE) signal with 11.5 dB peak-to-average ratio show that −42 dBc adjacent channel power ratio (ACLR) is achieved, with an average PAE of 30%, −47 dBc ACLR with an average PAE of 40% are obtained when using a WCDMA signal with 6.6 dB peak-to-average ratio (PAR).

Download Full-text

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078711000353 ◽

2011 ◽

Vol 3 (2) ◽

pp. 99-105 ◽

Cited By ~ 5

Author(s):

Dixian Zhao ◽

Ying He ◽

Lianming Li ◽

Dieter Joos ◽

Wim Philibert ◽

...

Keyword(s):

Output Power ◽

Power Amplifier ◽

Peak Power ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

60 Ghz ◽

Power Combiner ◽

Power Added Efficiency ◽

Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

Download Full-text

A Broadband Asymmetrical GaN MMIC Doherty Power Amplifier with Compact Size for 5G Communications

Electronics ◽

10.3390/electronics10030311 ◽

2021 ◽

Vol 10 (3) ◽

pp. 311

Author(s):

Peisen Cheng ◽

Quan Wang ◽

Wei Li ◽

Yeting Jia ◽

Zhichao Liu ◽

...

Keyword(s):

Output Power ◽

Power Amplifier ◽

Integrated Circuit ◽

Power Divider ◽

Total Power ◽

Design System ◽

Power Added Efficiency ◽

Matching Networks ◽

Compact Size ◽

Doherty Power Amplifier

This paper proposes a broadband asymmetrical monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) using 0.25-μm gallium-nitride process with a compact chip size of 2.37 × 1.86 mm2 for 5G communication. It adopts an unequal Wilkinson’s power divider with a ratio of 2.5:1, where 71.5% of the total power is transferred to the main amplifier for higher gain. Different input matching networks are used to offset phase difference while completing impedance conversion. This design also applies a novel topology to solve the problem of large impedance transformer ratio (ITR) in conventional DPA, and it optimizes the ITR from 4:1 to 2:1 for wider band. Moreover, most of the components of the DPA including power divider and matching networks use lumped inductors and capacitors instead of long transmission line (TL) for a smaller space area. The whole circuit is designed and simulated using Agilent’s advanced design system (ADS). The simulated small-signal gain of DPA is 8–11 dB and the saturation output power is more than 39.5 dBm with 800 MHz band from 4.5 GHz to 5.3 GHz. At 6-dB output power back-off, the DPA demonstrates 38–41.3% power added efficiency (PAE), whereas 44–54% PAE is achieved at saturation power.

Download Full-text

12 dBm OCP1dB Millimeter-wave 28 nm CMOS Power Amplifier using Integrated Transformers

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v11i2.434 ◽

2016 ◽

Vol 11 (2) ◽

pp. 97-105

Author(s):

Bernardo Leite ◽

Eric Kerhervé ◽

Didier Belot

Keyword(s):

Power Amplifier ◽

Rejection Rate ◽

Cmos Technology ◽

Common Source ◽

Output Stage ◽

Power Added Efficiency ◽

Matching Networks ◽

Insertion Losses ◽

Better Than ◽

28 Nm

This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and uses one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns are sized to provide low insertion losses and high common-mode rejection rate (CMRR) as well as integrating the input and output matching networks. The designed baluns achieve minimum insertion losses better than 0.8 dB and CMRR superior to 27 dB. The output-stage transistors have a measured 1 dB output compression point (OCP1dB) of 10.2 dBm, 10.1 dB gain and peak power added efficiency (PAE) as high as 35%. Thanks to the transformers, the PA presents a compact implementation, occupying only 0.037 mm² on silicon. The fabricated PA achieves 12 dBm OCP1dB, 15.3 dB gain and peak PAE better than 20%.

Download Full-text

K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

Electronics ◽

10.3390/electronics10080890 ◽

2021 ◽

Vol 10 (8) ◽

pp. 890

Author(s):

Kyu-Jin Choi ◽

Jae-Hyun Park ◽

Seong-Kyun Kim ◽

Byung-Sung Kim

Keyword(s):

Output Power ◽

Power Amplifier ◽

Supply Voltage ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Common Source ◽

Output Resistance ◽

Power Added Efficiency ◽

High Output ◽

K Band

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

Download Full-text

A Ruggedness Improved Mobile Radio Frequency Power Amplifier Module with Dynamic Impedance Correction by Software Defined Atomization

Electronics ◽

10.3390/electronics8111317 ◽

2019 ◽

Vol 8 (11) ◽

pp. 1317 ◽

Cited By ~ 1

Author(s):

Jooyoung Jeon ◽

Myounggon Kang

Keyword(s):

Radio Frequency ◽

Power Amplifier ◽

Bias Voltage ◽

Integrated Circuit ◽

Complementary Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Impedance Change ◽

Load Impedance ◽

Power Added Efficiency

A ruggedness improved multi-band radio frequency (RF) power amplifier (PA) module applicable to mobile handsets, which are required to survive against a serious load impedance change under extreme power and bias conditions, is presented. In this method, the load impedance of PA is adaptively adjusted with a digitally controlled impedance corrector to keep the PA safe by performing a load mismatch detection. The impedance mismatch detector, impedance corrector, and other RF switches were all integrated into a single integrated circuit (IC) using silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS). For the verification purpose, a 2-stage hetero junction bipolar transistor (HBT) PA module adopting this method was fabricated. At a frequency of 1915 MHz, a collector bias voltage of 4.2 V, and over a wider range of load impedance variation between a VSWR of 1 and a VSWR of 5.5, it did not fail. When this technique was not applied with a voltage standing wave ratio (VSWR) range of 1 to 4, it resulted in an acceptable RF performance degradation of 1% power added efficiency (PAE) in envelope tracking (ET) mode. Moreover, it survived at a bias voltage 1V larger than when the technique was not applied for the same mismatch condition.

Download Full-text

Compact 20-W GaN Internally Matched Power Amplifier for 2.5 GHz to 6 GHz Jammer Systems

Micromachines ◽

10.3390/mi11040375 ◽

2020 ◽

Vol 11 (4) ◽

pp. 375

Author(s):

Min-Pyo Lee ◽

Seil Kim ◽

Sung-June Hong ◽

Dong-Wook Kim

Keyword(s):

Output Power ◽

Power Amplifier ◽

High Frequency ◽

Continuous Wave ◽

Low Frequency ◽

Single Layer ◽

Dielectric Constants ◽

High Electron ◽

Active Device ◽

Power Added Efficiency

In this paper, we demonstrate a compact 20-W GaN internally matched power amplifier for 2.5 to 6 GHz jammer systems which uses a high dielectric constant substrate, single-layer capacitors, and shunt/series resistors for low-Q matching and low-frequency stabilization. A GaN high-electron-mobility transistor (HEMT) CGH60030D bare die from Wolfspeed was used as an active device, and input/output matching circuits were implemented on two different substrates using a thin-film process, relative dielectric constants of which were 9.8 and 40, respectively. A series resistor of 2.1 Ω was chosen to minimize the high-frequency loss and obtain a flat gain response. For the output matching circuit, double λ/4 shorted stubs were used to supply the drain current and reduce the output impedance variation of the transistor between the low-frequency and high-frequency regions, which also made wideband matching feasible. Single-layer capacitors effectively helped reduce the size of the matching circuit. The fabricated GaN internally matched power amplifier showed a linear gain of about 10.2 dB, and had an output power of 43.3–43.9 dBm (21.4–24.5 W), a power-added efficiency of 33.4–49.7% and a power gain of 6.2–8.3 dB at the continuous-wave output power condition, from 2.5 to 6 GHz.

Download Full-text