scholarly journals An Optimized Structure of Split-Gate Resurf Stepped Oxide UMOSFET

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 745
Author(s):  
Runze Chen ◽  
Lixin Wang ◽  
Naixia Jiu ◽  
Hongkai Zhang ◽  
Min Guo
Keyword(s):  
Electric Field ◽  
Figure Of Merit ◽  
Field Effect Transistor ◽  
Regulatory Mechanism ◽  
Oxide Semiconductor ◽  
Optimal Parameters ◽  
Field Peak ◽  
Conventional Structure ◽  
Effect Transistor ◽  
Source Electrode

In this paper, a split-gate resurf stepped oxide with double floating electrodes (DFSGRSO) U-shape metal oxide semiconductor field-effect transistor (UMOSFET) is proposed. The floating electrodes are symmetrically distributed on both sides of the source electrode in the trench. The performance of the DFSGRSO UMOSFET with different size of floating electrodes is simulated and analyzed. The simulation results reveal that the floating electrodes can modulate the distribution of the electric field in the drift area, improving the performance of the device significantly. The breakdown voltage (BV) and figure of merit (FOM) of the DFSGRSO UMOSFET at optimal parameters are 23.6% and 53.1% higher than that of the conventional structure. In addition, the regulatory mechanism of the floating electrodes is analyzed. The electric field moves from the bottom of the trench to the middle of the drift area, which brings a new electric field peak. Therefore, the distribution of the electric field is more uniform for the DFSGRSO UMOSFET compared with the conventional structure.

scholarly journals A New Split Gate Resurf Stepped Oxide UMOSFET Structure with High Doped Epitaxial Layer for Improving Figure of Merit (FOM)

2020 ◽  
Vol 10 (21) ◽  
pp. 7895
Author(s):  
Runze Chen ◽  
Lixin Wang ◽  
Hongkai Zhang ◽  
Mengyao Cui ◽  
Min Guo
Keyword(s):  
Electric Field ◽  
Epitaxial Layer ◽  
Computer Aided Design ◽  
Figure Of Merit ◽  
Cost Effective ◽  
Oxide Semiconductor ◽  
Fabrication Procedure ◽  
Conventional Structure ◽  
Aided Design ◽  
Reduced Surface

The split gate resurf stepped oxide with highly doped epitaxial layer (HDSGRSO) UMOSFET has been proposed. The epitaxial layer of HDSGRSO u-shape metal oxide semiconductor field effect transistor (UMOSFET) has been divided into three parts: the upper epitaxial layer, the lower epitaxial layer and the middle epitaxial layer with higher doping concentration. The research shows that the reduced SURface field (RESURF) active has been enhanced due to the high doped epitaxial layer, which can modulate the electric field distribution and reduce the internal high electric field. Therefore, the HDGRSO UMOSFET has a higher breakdown voltage (BV), a lower on-state specific resistance (RSP) and a better figure of merit (FOM). According to the results of Technology Computer Aided Design (TCAD) simulations, the FOM (BV2/RSP) of HDSGRSO UMOSFET has been improved by 464%, and FOM (RSP × Qgd) of HDSGRSO UMOSFET has been reduced by 27.9% compared to the conventional structure, respectively, when the BV is 240 V. Furthermore, there is no extra special process required in this advanced fabrication procedure, which is relatively cost-effective and achievable.

scholarly journals Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Michael Loong Peng Tan
Keyword(s):  
Carbon Nanotube ◽  
Electric Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Unit Area ◽  
Gain Control ◽  
Oxide Semiconductor ◽  
Wide Range ◽  
Effect Transistor ◽  
Long Channel

Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density.

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

2015 ◽  
Vol 1096 ◽  
pp. 514-519
Author(s):  
Yue Hu ◽  
Hao Wang ◽  
De Wen Wang ◽  
Cai Xia Du ◽  
Miao Miao Ma ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Impurity Atoms ◽  
Surface Field ◽  
Field Peak ◽  
Effect Transistor

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

The Silicon Plates in Buried Oxide for Enhancement of the Breakdown Voltage in SOI MESFET

2014 ◽  
Vol 538 ◽  
pp. 58-61
Author(s):  
Amir Reza Estakhrian Haghighi ◽  
Mojtaba Mohamadi
Keyword(s):  
Electric Field ◽  
Field Distribution ◽  
Breakdown Voltage ◽  
Field Effect Transistor ◽  
Electric Field Distribution ◽  
Silicon On Insulator ◽  
Output Resistance ◽  
Buried Oxide ◽  
Conventional Structure ◽  
Effect Transistor

This paper introduces a novel SOI MESFET which enhancement breakdown voltage (VBR) by modifying electric field distribution. To achieve high enhancement of the VBR utilized three Silicon plates in buried oxide of the silicon on insulator metal semiconductor field effect transistor (SOI MESFET). This change in the SOI MESFET structure leads to controlled electric field distribution , increase VBR and Output Resistance (RO). The numerical simulation results show that the VBR of the Silicon Plates SOI MESFET (SP-SOI MESFET) structure improves by 50% compared with that of the conventional SOI MESFET (C-SOI MESFET) structure. As a result, the SP-SOI MESFET structure has superior electrical performances in comparison with the conventional structure.

Shielded Gate SiC Trench Power MOSFET with Ultra-Low Switching Loss

2018 ◽  
Vol 924 ◽  
pp. 765-769
Author(s):  
Xuan Li ◽  
Xing Tong ◽  
Alex Q. Huang ◽  
Shi Qiu ◽  
Xu She ◽  
...  
Keyword(s):  
Figure Of Merit ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Device Structure ◽  
Switching Speed ◽  
Effect Transistor ◽  
High Switching Speed ◽  
The Impact

A shielded gate trench silicon carbide (SiC) metal oxide semiconductor field effect transistor (SG-TMOS) is proposed and investigated by simulation in this paper. The impact of shielded gate design in SG-TMOS on Miller charge (Qgd) as well as conduction resistance (Ron) are comprehensively discussed, showing a tradeoff between Qgdand Ron. Furthermore, the Huang’s Figure of Merit (HFOM) of the SG-TMOS with reasonable design of SG is reduced more than 20%, compared with the conventional trench MOSFET (C-TMOS). Therefore, the proposed SG-TMOS is a competitive next generation device structure for ultra-high switching speed SiC MOSFET.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Sign in / Sign up

Export Citation Format

Share Document