scholarly journals A PWM/PFM Dual-Mode DC-DC Buck Converter with Load-Dependent Efficiency-Controllable Scheme for Multi-Purpose IoT Applications

Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 960
Author(s):  
Myeong Woo Kim ◽  
Jae Joon Kim
Keyword(s):  
Power Efficiency ◽  
Buck Converter ◽  
Maximum Efficiency ◽  
Switching Frequency ◽  
Cmos Process ◽  
Dual Mode ◽  
Pulse Frequency Modulation ◽  
Heavy Load ◽  
Iot Applications ◽  
Light Load

This paper presents a dual-mode DC-DC buck converter including a load-dependent, efficiency-controllable scheme to support multi-purpose IoT applications. For light-load applications, a selectable adaptive on-time pulse frequency modulation (PFM) control is proposed to achieve optimum power efficiency by selecting the optimum switching frequency according to the load current, thereby reducing unnecessary switching losses. When the inductor peak current value or converter output voltage ripple are considered in some applications, its on-time can be adjusted further. In heavy-load applications, a conventional pulse width modulation (PWM) control scheme is adopted, and its gate driver is structured to reduce dynamic current, preventing the current from shooting through the power switch. A proposed dual-mode buck converter prototype is fabricated in a 180 nm CMOS process, achieving its measured maximum efficiency of 95.7% and power density of 0.83 W/mm2.

Implementation and Design of Voltage-Mode PFM Control Buck Power Converter

2013 ◽  
Vol 860-863 ◽  
pp. 2390-2394
Author(s):  
Min Chin Lee ◽  
Ruey Wun Jan
Keyword(s):  
Supply Voltage ◽  
Pulse Frequency ◽  
Power Converter ◽  
Buck Converter ◽  
Switching Frequency ◽  
Cmos Process ◽  
Pulse Frequency Modulation ◽  
Better Regulation ◽  
Chip Size ◽  
Voltage Feedback

A lower power consumption, smaller output ripple and better regulation buck dcdc converter controlled by voltage feedback and pulse-frequency modulation (PFM) mode is implemented in this paper. The converter operating in discontinuous conduction mode (DCM) is designed and simulated using the TSMC 0.18μm 1P6M CMOS Process. Hspice simulation results show that, the buck converter having chip size with power dissipation about 0.68mW. This chip can operate with input supply voltage from 1.2V to 1.8V, and switching frequency from 249KHz () to 50KHz (), and its output voltage can stable at 1.0V and less than 110mV ripple voltage at maximum loading current 100 mA.

scholarly journals Active EMI Reduction Using Chaotic Modulation in a Buck Converter with Relaxed Output LC Filter

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 254 ◽  
Author(s):  
Van Nguyen ◽  
Hai Huynh ◽  
SoYoung Kim ◽  
Hanjung Song
Keyword(s):  
Electromagnetic Interference ◽  
Power Efficiency ◽  
Pulse Width Modulation ◽  
Buck Converter ◽  
Oxide Semiconductor ◽  
Switching Frequency ◽  
Cmos Process ◽  
Reference Case ◽  
Ramp Generator ◽  
Chaotic Mode

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case.

Research on Multi-Mode Controller of Switching Power Supply

2014 ◽  
Vol 568-570 ◽  
pp. 1217-1220
Author(s):  
Shu Lin Liu ◽  
Li Li Qi
Keyword(s):  
Power Supply ◽  
Switching Frequency ◽  
Switching Power Supply ◽  
Load Range ◽  
Heavy Load ◽  
Operating Modes ◽  
Switching Power ◽  
Advantages And Disadvantages ◽  
Switching Losses ◽  
Light Load

In order to improve the efficiency of the switching power supply in whole load range, the controller with PWM, PFM and BURST operating modes is designed in this paper, which changes the operation mode automatically according to the load. The operating principle and the advantages and disadvantages of the three operating modes are analyzed and compared. PWM mode is used in heavy load; PFM mode is used in light load to reduce switching losses by reducing the switching frequency and BURST mode is used at the standby time to further reduce switching losses. The main control module is designed and simulation results verify the feasibility of the designed circuit.

A Near-Threshold Voltage Startup Monolithic Boost Converter with Adaptive Sleeping Time Control

2016 ◽  
Vol 26 (04) ◽  
pp. 1750063 ◽  
Author(s):  
Lianxi Liu ◽  
Yiyang Zhou ◽  
Junchao Mu ◽  
Xufeng Liao ◽  
Zhangming Zhu ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Input Voltage ◽  
Boost Converter ◽  
Switching Frequency ◽  
Cmos Process ◽  
Sleeping Time ◽  
Time Control ◽  
Soft Start ◽  
Light Load ◽  
Near Threshold

A novel near-threshold voltage startup monolithic boost converter is presented in this paper using an adaptive sleeping time control (ASTC) scheme for low-power applications. The proposed ASTC scheme can promote the power efficiency of the current-mode boost converter under light load by automatically adjusting the sleep time of the converter, and the converter's quiescent current drops down to 4[Formula: see text][Formula: see text]A during the sleeping period. In addition, a new soft-start method is introduced to make the boost converter start up with a near-threshold input voltage. The proposed boost converter was fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a small chip area of 0.50[Formula: see text][Formula: see text][Formula: see text]mm. Experimental results show that the boost converter achieves the minimum 0.5-V startup voltage when the output voltage is set to 1.8[Formula: see text]V. After startup, the input voltage range can be expanded from 0.3[Formula: see text]V to 1.5[Formula: see text]V with a switching frequency of 1[Formula: see text]MHz. In addition, a peak efficiency of 94% and a minimum efficiency of 81% are measured at the 1.5-V input voltage as the load current ranges from 0.1[Formula: see text]mA to 100[Formula: see text]mA.

A Dual-Mode High-Voltage High-Efficiency Peak-Current-Mode Asynchronous Buck Converter

2016 ◽  
Vol 25 (11) ◽  
pp. 1650136 ◽  
Author(s):  
Zhaohan Li ◽  
Yongcheng Ji ◽  
Shu Yang ◽  
Yuchun Chang
Keyword(s):  
High Voltage ◽  
High Efficiency ◽  
Load Condition ◽  
Reducing Power ◽  
Current Mode ◽  
Buck Converter ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Peak Current ◽  
Light Load

This paper proposes a high-voltage high-efficiency peak-current-mode asynchronous DC–DC step-down converter operating with dual operation modes. The asynchronous buck converter achieves higher efficiency in light load condition compared to synchronous buck converters. Furthermore, the proposed buck converter switches operation mode automatically from pulse-width modulation (PWM) mode to pulse-skipping mode (PSM). By reducing power MOS on-state resistance and optimizing rise/fall time of switches, the proposed buck converter also obtains high efficiency under heavy load condition. The maximum efficiency of the proposed buck converter is 92.9%, implemented with 0.35[Formula: see text][Formula: see text]m BCDMOS 2P3M process, and the total size is 1.1[Formula: see text] 1.2[Formula: see text]mm2. The input range and output range of the converter are 6–30 V, and ([Formula: see text]–3) V, respectively, with the maximum output current of 3 A. Moreover, its built-in current loop leads to good transient response characteristics. Therefore, it can be used widely in communication system and 12 V/24 V distributed power system.

scholarly journals Three-Output Flyback Converter with Synchronous Rectification for Improving Cross-Regulation and Efficiency

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 430
Author(s):  
Chung-Ming Leng ◽  
Huang-Jen Chiu
Keyword(s):  
Maximum Efficiency ◽  
Heavy Load ◽  
Leakage Inductance ◽  
Flyback Converter ◽  
Conduction Loss ◽  
Analog Ic ◽  
Light Load ◽  
Load Imbalance ◽  
Extreme Load ◽  
Synchronous Rectification

This paper proposes a single stage alternating current/direct current (AC/DC) flyback converter which contains three output windings with synchronous rectification (SR) function to achieve better cross-regulation and efficiency. Because the three output windings are stacked in a series structure and use synchronous rectification instead of diode rectification, the forward conduction loss of the diode can be eliminated, and the current of each winding can flow bilaterally. Therefore, the energy of leakage inductance can be dissipated through heavy load winding without transient overvoltage in light load winding. Compared with existing methods in the literature, the proposed converter can be realized by simple analog IC with fewer winding turns. Finally, under the extreme load imbalance condition, the cross-regulation is still within ±2.26%. The maximum efficiency of the proposed converter reaches 87%, which is about 3% higher than the conventional Schottky diode solution’s efficiency. The circuit structure and operation principle are described. A practical prototype and experiment results are implemented to verify the feasibility of the proposed converter.

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator

2017 ◽  
Vol 26 (12) ◽  
pp. 1750193 ◽  
Author(s):  
Xin Cheng ◽  
Hongyu Liang ◽  
Longjie Du ◽  
Zhang Zhang ◽  
Maoxiang Yi ◽  
...  
Keyword(s):  
Transient Response ◽  
Cmos Process ◽  
Heavy Load ◽  
Ultra Low Power ◽  
Chip Area ◽  
Error Amplifier ◽  
Light Load ◽  
Gain Stage ◽  
Ldo Regulator ◽  
Overshoot And Undershoot

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a chip area of 0.06[Formula: see text]mm2. The LDO is measured to output a stable voltage at 1.6[Formula: see text]V with a quiescent power of 1.8[Formula: see text][Formula: see text]W. The experimental results also show a good transient response.

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