scholarly journals Shaft Voltage Reduction Method Using Carrier Wave Phase Shift in IPMSM

Energies ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 6924
Author(s):  
Jun-Hyuk Im ◽  
Yeol-Kyeong Lee ◽  
Jun-Kyu Park ◽  
Jin Hur

Common-Mode Voltage (CMV) induces shaft voltage and bearing current due to the electrical interaction with the parasitic capacitance of the motor. CMV, shaft voltage, and bearing current are considered the major causes of bearing fault. Motor fault in a traction system poses a risk of accidents. Therefore, it is necessary to reduce the CMV and the shaft voltage to ensure the reliability of the bearing. However, some existing CMV reduction methods are based on asynchronized space vector pulse width modulation (SVPWM), which will cause unacceptable harmonic distortion at a low switching frequency. Alternatively, some CMV reduction methods based on synchronized SVPWM burden the processor because they require a lot of calculation. In this paper, the method to reduce CMV and shaft voltage is proposed using carrier wave phase shift in SVPWM. CMV is explained in traditional SVPWM, and CMV is reduced by shifting the carrier wave phase of one phase. The simulation model is constructed through MATLAB/SIMULINK and Maxwell 2D/Twin Builder. Considering the proposed method, CMV, shaft voltage, and bearing current are analyzed by an equivalent circuit model. Moreover, the output torque behaviors with different input currents are analyzed through the simulation.

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 466
Author(s):  
Pawel Szczepankowski ◽  
Natalia Strzelecka ◽  
Enrique Romero-Cadaval

This article presents three variants of the Pulse Width Modulation (PWM) for the Double Square Multiphase type Conventional Matrix Converters (DSM-CMC) supplying loads with the open-end winding. The first variant of PWM offers the ability to obtain zero value of the common-mode voltage at the load’s terminals and applies only six switches within the modulation period. The second proposal archives for less Total Harmonic Distortion (THD) of the generated load voltage. The third variant of modulation concerns maximizing the voltage transfer ratio, minimizing the number of switching, and the common-mode voltage cancellation. The discussed modulations are based on the concept of sinusoidal voltage quadrature signals, which can be an effective alternative to the classic space-vector approach. In the proposed approach, the geometrical arrangement of basic vectors needed to synthesize output voltages is built from the less number of vectors, which is equal to the number of the matrix converter’s terminals. The PWM duty cycle computation is performed using only a second-order determinant of the voltages coordinate matrix without using trigonometric functions. A new approach to the PWM duty cycles computing and the load voltage synthesis by 5 × 5 and 12 × 12 topologies has been verified using the PSIM simulation software.


2012 ◽  
Vol 591-593 ◽  
pp. 1579-1584
Author(s):  
Jyh Wei Chen ◽  
Huan Fu Lin

A grid-connected parallel inverter with interleaved phase shift is proposed in this paper. The synchronous are generated by the master module to achieve interleaving phase shift PWM for the parallel inverters connected to grid-tied system that make the inverter to output current to the power line and share the load. TI TMS320F2812 DSP is used for system feedback control with voltage and current by using A/D converters to generate the output current close to sine wave. The expected output current values are determined by the master module and transmitted via CAN (Control area network) between inverter modules. The grid-tied system uses zero-voltage-detection circuit to synchronize the inverter currents with grid voltage. For each switching period, PWM voltage of two inverters are interleaved to reduce the total output current ripple so that the switching frequency can be reduced and the power system EMI problem can be alleviated as well. The experiment results are provided to verify the performance of the proposed system to reduce output current harmonic distortion.


Multilevel inverters are widely used for high power and high voltage applications. The performance of multilevel inverters are superior to conventional two level inverters in terms of reduced total harmonic distortion, higher dc link voltages, lower electromagnetic interference and increased quality in the output voltage waveform. This paper presents a single phase hybrid eleven level multilevel inverter topology with reduced switch count to compensate the above mentioned disadvantages. This paper also presents various high switching frequency based multi carrier pulse width modulation strategies such as Phase Disposition PWM Strategy (PDPWM), Phase Opposition and Disposition PWM Strategy (PODPWM), Alternate Phase opposition Disposition PWM (APODPWM), Carrier Overlapping PWM (COPWM), Variable frequency carrier PWM (VFPWM), Third Harmonic Injection PWM (TFIPWM) applied to the proposed eleven level multilevel inverter and is analyzed for RL load. FFT analysis is carried out and total harmonic distortion, fundamental output voltage are calculated. Simulation is carried out in MATLAB/SMULINK.


Energies ◽  
2020 ◽  
Vol 13 (15) ◽  
pp. 3884
Author(s):  
Jian Zheng ◽  
Mingcheng Lyu ◽  
Shengqing Li ◽  
Qiwu Luo ◽  
Keyuan Huang

Aiming at the problem of large magnitude and high frequency of common-mode voltage (CMV) when space vector pulse width modulation (SVPWM) is used in a three-phase motor fed by a two-level voltage source inverter, a common-mode reduction SVPWM (CMRSVPWM) is studied. In this method, six new sectors are obtained by rotating six sectors of conventional SVPWM by 30°. In odd-numbered sectors, only three non-zero vectors with odd subscripts are used for synthesis, while in even-numbered sectors, only three non-zero vectors with even subscripts are used for synthesis. The actuation durations of three non-zero vectors in each switching period in each sector are given. Simulation and experimental results show that, compared with the conventional SVPWM, the CMV magnitude of CMRSVPWM is reduced by 66.67% and the CMV frequency of CMRSVPWM is reduced from the original switching frequency to the triple fundamental frequency. At the same time, the current, torque and speed of the motor are still good.


Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1440 ◽  
Author(s):  
Mehrdad Mahmoudian ◽  
Eduardo M. G. Rodrigues ◽  
Edris Pouresmaeil

Transformerless inverters are the economic choice as power interfaces between photovoltaic (PV) renewable sources and the power grid. Without galvanic isolation and adequate power convert design, single-phase grid connected inverters may have limited performance due to the presence of a significant common mode ground current by creating safety issues and enhancing the negative impact of harmonics in the grid current. This paper proposes an extended H6 transformerless inverter that uses an additional power switch (H7) to improve common mode leakage current mitigation in a single-phase utility grid. The switch with a diode in series connection aims to make an effective clamp of common mode voltage at the DC link midpoint. The principles of operation of the proposed structure with bipolar sinusoidal pulse width modulation (SPWM) is presented and formulated. Laboratory tests’ performance is detailed and evaluated in comparison with well-known single-phase transformer-less topologies in terms of power conversion efficiency, total harmonic distortion (THD) level, and circuit components number. The studied topology performance evaluation is completed with the inclusion of reactive power compensation functionality verified by a low-power laboratory implementation with 98.02% efficiency and 30.3 mA for the leakage current.


Author(s):  
R. Palanisamy ◽  
V. Sinmayee ◽  
K. Selvakumar ◽  
K. Vijayakumar

<p>In this paper a novel 5 switch seven level DC-AC inverter is being proposed. The proposed multilevel inverter uses reduced number of switches as compared to the switches used in the conventional multilevel inverter. The inverter has been designed to generate a 7 level AC output using 5 switches. The voltage stress on each of the switches as well as the switching losses is found to be less, minimized common mode voltage (CMV) level and reduced total harmonic distortion. The proposed 7-level inverter topology has four dc sources, which is energized through the PV system. Proposed inverter is controlled with help of multicarrier sinusoidal pulse width modulation (MCSPWM).The simulation and hardware results were verified using matlab simulink and dspic microcontroller respectively.</p>


Author(s):  
S.Z. Mohammad Noor ◽  
N. Rosmizi ◽  
N. Aminudin ◽  
Faranadia A.H

<p>This work presents investigation of passive filter performance on three-phase inverter with 180° conduction mode. The simulation model of the inverter is developed by using MATLAB/Simulink. The power circuit used Insulated Gate Bipolar Transistor (IGBT) as switching device. The inverter is controlled by using bipolar Sinusoidal Pulse Width Modulation (SPWM) technique. The IGBT was set to 25 kHz for switching frequency (fs). Three types of passive filters which are LC, RC and PI filters are used to investigate the ability to remove the unwanted signal that occurred on the inverter. The result is analyzed based on the performances of output filter in term of Total Harmonic Distortion in voltage (THD<sub>v</sub>), current (THD<sub>i</sub>), shape of output voltage and current. The THD must be less than 5% at rated inverter output voltage or current by referring to IEC 61727 Standard. The passive filter is modeled in MATLAB/Simulink environment to study the characteristics and performance of the filters.</p>


In this paper, a novel approach is proposed to reduce the impact of harmonics in the high-power medium-voltage squirrel-cage induction motor. An inverter with a minimum switching frequency is required for this load type to reduce the snubber and switching losses. Phase-shifting transformer is selected as an interface between the three-phase supply and the inverter. This is to reduce the impact of low order harmonics and consequently reducing total harmonic distortion (THD). Selective harmonic-elimination pulse width modulation (SHEPWM) is employed as a control technique in the inverter to eliminate specific low-order harmonics. Thereby, many low order harmonics are reduced further. By this way the THD of the system is reduced significantly and consequently the better and cleaner energy is obtained. In this research, PSpice simulation verified by MATLAB is used to estimate the harmonics content of the currents in high-power medium voltage induction motor.


Author(s):  
V. Mohan ◽  
N. Stalin ◽  
S. Jeevananthan

The pulse width modulated voltage source inverters (PWM-VSI) dominate in the modern industrial environment. The conventional PWM methods are designed to have higher fundamental voltage, easy filtering and reduced total harmonic distortion (THD). There are number of clustered harmonics around the multiples of switching frequency in the output of conventional sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) inverters. This is due to their fixed switching frequency while the variable switching frequency makes the filtering very complex. Random carrier PWM (RCPWM) methods are the host of PWM methods, which use randomized carrier frequency and result in a harmonic profile with well distributed harmonic power (no harmonic possesses significant magnitude and hence no filtering is required). This paper proposes a chaos-based PWM (CPWM) strategy, which utilizes a chaotically changing switching frequency to spread the harmonics continuously to a wideband and to reduce the peak harmonics to a great extent. This can be an effective way to suppress the current harmonics and torque ripple in induction motor drives. The proposed CPWM scheme is simulated using MATLAB / SIMULINK software and implemented in three phase voltage source inverter (VSI) using field programmable gate array (FPGA).


Author(s):  
Mohd Shafie Bakar ◽  
Nasrudin Abd. Rahim ◽  
Hamdan Daniyal ◽  
Kamarul Hawari Ghazali

On the basis of a conventional Z-source inverter, this paper presents an extension of the existing study about a driving scheme implementation of a simple boost pulse width modulation under open loop system for five phase two level system. The impact of design parameter (fixed modulation index and switching frequency) versus performance parameter (capacitor voltage, inductor current, total harmonic distortion and DC link voltage) are studied and analysed. To validate the advantages of Z-source five-phase inverter, the driving scheme are simulated using Matlab/Simulink and verified with real-time target board eZdsp<sup>TM</sup> TMS320F28335. From the study, it was found that under specified modulation index and switching frequency, the THD of an output current fulfilled the EN61000-3-2 standard.


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