scholarly journals A Time-Domain z−1 Circuit with Digital Calibration

2022 ◽  
Vol 12 (1) ◽  
pp. 3
Author(s):  
Orfeas Panetas-Felouris ◽  
Spyridon Vlassis
Keyword(s):  
Time Domain ◽  
Supply Voltage ◽  
Input Pulse ◽  
Digital Calibration ◽  
Worst Case ◽  
Temperature Variations ◽  
Chip Temperature ◽  
Technology Process ◽  
Capacitor Voltage ◽  
Better Than

This paper presents a novel circuit of a z−1 operation which is suitable, as a basic building block, for time-domain topologies and signal processing. The proposed circuit employs a time register circuit which is based on the capacitor discharging method. The large variation of the capacitor discharging slope over technology process and chip temperature variations which affect the z−1 accuracy is improved using a novel digital calibration loop. The circuit is designed using a 28 nm Samsung FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate the theoretical analysis presenting a variation of capacitor voltage discharging slope less than 5% over worst-case process corners for temperature between 0 °C and 100 °C while consuming only 30 μA. Also, the worst-case accuracy of z−1 operation is better than 33 ps for input pulse widths between 5 ns and 45 ns presenting huge improvement compared with the uncalibrated operator.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

scholarly journals Managing contamination delay to improve Timing Speculation architectures

2016 ◽  
Vol 2 ◽  
pp. e79 ◽  
Author(s):  
Naga Durga Prasad Avirneni ◽  
Prem Kumar Ramesh ◽  
Arun K. Somani
Keyword(s):  
Performance Improvement ◽  
Short Path ◽  
Performance Enhancement ◽  
Propagation Delay ◽  
Performance Impact ◽  
Worst Case ◽  
Circuit Delay ◽  
Timing Speculation ◽  
Better Than

Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.

scholarly journals Hybrid ARIMA and Neural Network Modelling Applied to Telecommunications in Urban Environments in the Amazon Region

2020 ◽  
Vol 2020 ◽  
pp. 1-14
Author(s):  
Ramz L. Fraiha Lopes ◽  
Simone G. C. Fraiha ◽  
Vinicius D. Lima ◽  
Herminio S. Gomes ◽  
Gervásio P. S. Cavalcante
Keyword(s):  
Neural Network ◽  
Moving Average ◽  
Urban Environments ◽  
Digital Television ◽  
Network Modelling ◽  
Worst Case ◽  
Autoregressive Integrated Moving Average ◽  
Neural Network Modelling ◽  
Better Than

This study explores the use of a hybrid Autoregressive Integrated Moving Average (ARIMA) and Neural Network modelling for estimates of the electric field along vertical paths (buildings) close to Digital Television (DTV) transmitters. The work was carried out in Belém city, one of the most urbanized cities in the Brazilian Amazon and includes a case study of the application of this modelling within the subscenarios found in Belém. Its results were compared with the ITU recommendations P. 1546-5 and proved to be better in every subscenario analysed. In the worst case, the estimate of the model was approximately 65% better than that of the ITU. We also compared this modelling with a classic modelling technique: the Least Squares (LS) method. In most situations, the hybrid model achieved better results than the LS.

ON-LINE SUPPLY VOLTAGE SCALING BASED ON IN SITU DELAY MONITORING TO ADAPT FOR PVTA VARIATIONS

2012 ◽  
Vol 21 (08) ◽  
pp. 1240027 ◽  
Author(s):  
MARTIN WIRNSHOFER ◽  
NASIM POUR ARYAN ◽  
LEONHARD HEISS ◽  
DORIS SCHMITT-LANDSIEDEL ◽  
GEORG GEORGAKOS
Keyword(s):  
Closed Loop ◽  
Supply Voltage ◽  
Average Power ◽  
Voltage Scaling ◽  
Error Rates ◽  
Design Flow ◽  
Chain Model ◽  
Worst Case ◽  
On Line

The presented Pre-Error Adaptive Voltage Scaling (AVS) approach tunes the supply voltage of digital circuits dependent on the present Process, Voltage and Temperature variations as well as Aging (PVTA). By exploiting unused timing margin, produced by state-of-the-art worst-case designs, power consumption is minimized. Timing information of the circuit is obtained by in situ delay monitors (Pre-Error flip-flops), detecting late-arriving signals (pre-errors) in critical paths. Based on the occurrence of pre-errors, the voltage is adjusted by a low-overhead control unit connected to the on-chip voltage regulator. As the voltage is adapted during normal circuit operation (on-line), the randomness of the applied input pattern has to be considered. We developed a Markov chain model, based on transistor level simulations, to describe the resulting statistics of the closed-loop voltage control. With this model, the risk of overcritical voltage reductions and the effect of global and local variations on the closed-loop control can be analyzed. For an arithmetic circuit, synthesized in an industrial 65nm design-flow, an average power saving of 23% (including all overheads) is achieved for very low error rates below 1E-11.

Mooring Analysis of a Turret Moored FPSO in a Squall Environment

2015 ◽  
Author(s):  
Robert Oberlies ◽  
Amitava Guha ◽  
Scott Slocum
Keyword(s):  
Dynamic Response ◽  
Time Domain ◽  
Sensitivity Study ◽  
West African ◽  
Load Case ◽  
The West ◽  
Worst Case ◽  
Input Parameters ◽  
Computationally Intensive ◽  
Transient Dynamic Response

The transient dynamic response of a FPSO in a squall environment is dependent on several input parameters. Because the response’s dependence on these input parameters is unclear prior to performing the analysis, a large number of parameter combinations need to be considered to find the combination that gives a worst-case load or response as required by reference [1]. Because the required time-domain simulations are computationally intensive, there is often a practical need to limit the number of simulations that are performed, raising questions about how many are necessary to meet the analysis objectives. This study investigates the effect of different squall scenarios on a turret moored FPSO in the West African offshore environment. A large number of cases with selected vessel headings, squall types, squall approach directions and vessel drafts are studied and parameters affecting the critical mooring loads and turret positions are identified. Possible reductions in the load case matrix along with a sensitivity study of a few parameters affecting the results are also discussed.

l 1 Controller Design for a High-Order 5-Pool Irrigation Canal System

2003 ◽  
Vol 125 (4) ◽  
pp. 639-645 ◽  
Author(s):  
Pierre-Olivier Malaterre ◽  
Mustafa Khammash
Keyword(s):  
Time Domain ◽  
Controller Design ◽  
Mimo System ◽  
State Space Model ◽  
High Order ◽  
Irrigation Canal ◽  
Phase System ◽  
L1 Norm ◽  
Worst Case ◽  
Nonminimum Phase

The aim of this work is to present an application of recent methods for solving the l1 design problem, based on the Scaled-Q approach, on a high-order, nonminimum phase system. We start by describing the system which is an open-channel hydraulic system (e.g., an irrigation canal). From the discretization and linearization of the set of two partial-derivative equations, a state-space model of the system is generated. This model is a high-order MIMO system (five external perturbations w, five control inputs u, 10 controlled outputs z, five measured outputs y, 65 states x) and is nonminimum phase. A controller is then designed by minimizing the l1 norm of the impulse response of the transfer matrix between the perturbations w and the outputs z. Time-domain constraints are added into the minimization problem in order to force integrators into the controller. The numerical resolution of the problem proved to be efficient, despite of the characteristics of the system. The obtained results are compared in the time-domain to classical PID and LQG controllers on the nonlinear system. The results are good in terms of performance and robustness, in particular for the rejection of the worst-case perturbation.

Developments in African Governance since the Cold War: Beyond Cassandra and Pollyanna

2010 ◽  
Vol 53 (2) ◽  
pp. 49-76 ◽  
Author(s):  
Hazel McFerson
Keyword(s):  
Cold War ◽  
Civil Conflict ◽  
External Pressure ◽  
Economic Governance ◽  
Ethnic Conflicts ◽  
African Countries ◽  
Worst Case ◽  
The Cold War ◽  
Institutional Capacity Building ◽  
Better Than

Abstract:Twenty years ago, most African countries seemed permanently mired in malgovernance and repression. The end of the Cold War triggered two contrasting developments: governance improvement associated with the end of superpower competition, and deterioration caused by the resurgence of suppressed ethnic conflicts. Based on a variety of evidence, three subperiods can be identified: fragile governance progress from 1989 to 1995; backsliding associated largely with civil conflict between 1996 and 2002; and resumption of progress in recent years. These broad trends mask major intercountry differences—with Ghana the best-known case of improvement and Zimbabwe the worst case of reversal. Overall, African governance is now somewhat better than it was two decades ago. However, the progress is fragile, and improvements in administrative and economic governance have lagged behind those on the political front. Consolidating democracy will thus require institutional capacity building through a combination of appropriate civil society efforts and constructive external pressure to strengthen accountability.

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