scholarly journals FPGA Implementation of Archery Target Detection using Color Sequence Recognition Algorithm

2019 ◽  
Vol 8 (2S8) ◽  
pp. 1391-1397
Keyword(s):  
Central Region ◽  
Color Space ◽  
Recognition Algorithm ◽  
Fpga Implementation ◽  
Target Distance ◽  
Color Classification ◽  
Sequence Recognition ◽  
Field Programmable ◽  
Image Pixels ◽  
Color Sequence

In this paper, an implementation of image processing methods to extract and recognize a standard tri-colored archery target to a field-programmable gate array is demonstrated. Detection and recognition of the archery target was never been done on an FPGA platform. The platform used to realize the design was the ZedBoard™ Development Kit equipped with Xilinx Zynq®-7000 All Programmable system on chip. The algorithms used to extract the central region is based on color classification in HSV color space. Once each image pixels are classified, the color sequence recognition algorithm attempts to look for the target and extract the central region of the archery target if present. Image filtering techniques and analysis such as morphological filtering and contour feature analysis are used to properly identify the shape and location of the extracted pixels. Discussed next is the implementation of the algorithm both in the software and hardware aspects and a comparison between their response time and accuracy is demonstrated. There was about two-fold decrease in processing time when FPGA implementation was deployed. The accuracy of the system was also tested and able to reach an accuracy of 96.67% for near target distance. For far target distance, the accuracy degraded to 88.33% but the system has managed to maintain its specificity value despite the noise becoming dominant for smaller region occupied by the target.

scholarly journals Colour Recognition Algorithm Based on Colour Mapping Knowledge for Wooden Building Image

2022 ◽  
Vol 2022 ◽  
pp. 1-11
Author(s):  
Siyi Jia ◽  
Heng Chen
Keyword(s):  
Mutual Influence ◽  
Block Diagram ◽  
Recognition Algorithm ◽  
Linear Mapping ◽  
Display Device ◽  
Mapping Algorithm ◽  
Image Reproduction ◽  
Reproduction Process ◽  
Mapping Technology ◽  
Image Pixels

In the cross-media image reproduction technology, the accurate transfer and reproduction of colour between different media are an important issue in the reproduction process, and the colour mapping technology is the key technology to effectively maintain the image details and improve the level of colour reproduction. Wooden structure in the image colour and colour piece is different, the image of each colour of visual perception is not independent, and every colour in the image pixels is affected by the surrounding pixels, but in the process of image map, without thinking of the pixel space, adjacent pixels of mutual influence in particular, do not let a person particularly be satisfied with the resulting map figure. In the process of image processing by traditional colour mapping algorithm, the colour distortion caused by colour component is ignored and the block diagram of colour mapping system is constructed. With the continuous development of mapping recognition algorithms, the maximum and minimum brightness values in the image are mapped to the maximum and minimum brightness values of the display device by linear mapping algorithm according to the flow of the established recognition algorithm. By establishing the colour adjustment method of the colour mapping image, the processing effect of the mapping algorithm is analysed. The results show that the brightness deviation of the image is reduced and the colour resolution is improved by the colour brightness compensation.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

scholarly journals FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

2019 ◽  
Vol 2019 ◽  
pp. 1-17 ◽  
Author(s):  
Nitish Das ◽  
Aruna Priya P
Keyword(s):  
Barrier Function ◽  
Gradient Descent ◽  
Finite State Machine ◽  
Fpga Implementation ◽  
Greedy Heuristic ◽  
Logarithmic Barrier Function ◽  
Finite State ◽  
Field Programmable ◽  
Significant Area ◽  
Logarithmic Barrier

Recently, the Reconfigurable FSM has drawn the attention of the researchers for multistage signal processing applications. The optimal synthesis of Reconfigurable finite state machine with input multiplexing (Reconfigurable FSMIM) architecture is done by the iterative greedy heuristic based Hungarian algorithm (IGHA). The major problem concerning IGHA is the disintegration of a state encoding technique. This paper proposes the integration of IGHA with the state assignment using logarithmic barrier function based gradient descent approach to reduce the hardware consumption of Reconfigurable FSMIM. Experiments have been performed using MCNC FSM benchmarks which illustrate a significant area and speed improvement over other architectures during field programmable gate array (FPGA) implementation.

scholarly journals Coloration Characteristic and Population Genetic Analysis of Wild-Captured Giant Tiger Shrimp (Penaeus monodon) from Aceh Timur

2018 ◽  
Vol 23 (3) ◽  
pp. 123
Author(s):  
Indriatmoko Indriatmoko ◽  
Dimas A. Hedianto ◽  
Sari Budi Moria ◽  
Didik WH Tjahjo
Keyword(s):  
Penaeus Monodon ◽  
Color Space ◽  
Quantitative Information ◽  
Color Analysis ◽  
Population Genetic Analysis ◽  
Tiger Shrimp ◽  
16S Rdna Pcr ◽  
Aceh Province ◽  
Image Pixels ◽  
Space Data

Giant tiger shrimp (Penaeus monodon) has become a prime commodity in Indonesia which was produced by aquaculture and capture fisheries activities. Aceh Province, in this case mostly represented by Aceh Timur District, was well-known as the center of wild-captured-adult giant tiger shrimp. Several previous investigations had proved for its high-quality shrimp spawner in producing good eggs in quality and quantity under artificial spawning condition. Two main interesting points of wild giant tiger shrimp from Aceh Timur came from their coloration and population clusters. This report was aimed to provide that information pre-preliminary and highlighted quantitative information of coloration characteristic through RGB (Red Green Blue) and CIE Lab color space data analysis, as well as, 16S rDNA-PCR-RFLP genetic comparison among four population clusters in Aceh Timur Waters. The color analysis resulted in significant differences between wild-captured and pond-cultured giant tiger shrimp which produced R value 0.1524±0.0091 and 0.1268±0.0004, respectively. Total pixel analysis through L* a* b* color space has distinguished detailed differentiation between wild-captured and pond-cultured giant tiger shrimp acquired images. It is known that most of the wild-captured image pixels were concentrated in quadrant I (+a, +b) while pond-cultured in quadrant II (-a, +b) and III (-a, -b).Genotyping of represented samples from 4 population clusters, i.e. Aceh Tamiang, Langsa, Peudawa, and Julok produce 2 haplotype composite, AAA and AAB. Among 4 clusters, it was found that Julok has become the only cluster which has a different haplotype composite ratio (1:1) (D 0.0348, V 0,9501) from the others (4:1)(V 0.9504).

Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

scholarly journals FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF THE DYNAMIC TIME WARPING ALGORITHM FOR SPEECH RECOGNITION

2017 ◽  
Vol 10 (13) ◽  
pp. 248
Author(s):  
John Sahaya Rani Alex ◽  
Mitali Bhojwani
Keyword(s):  
Speech Recognition ◽  
Field Programmable Gate Array ◽  
Dynamic Time Warping ◽  
Recognition Algorithm ◽  
Consumer Electronics ◽  
Time Warping ◽  
Time To Market ◽  
Computing Power ◽  
Field Programmable ◽  
Dynamic Time

Objective of this research is to implement a speech recognition algorithm in smaller form factor device. Speech recognition is an extensively used inmobile and in numerous consumer electronics devices. Dynamic time warping (DTW) method which is based on dynamic programming is chosen tobe implemented for speech recognition because of the latest trend in evolving computing power. Implementation of DTW in field-programmable gatearray is chosen for its featured flexibility, parallelization and shorter time to market. The above algorithm is implemented using Verilog on Xilinx ISE.The warping cost is less if the similarity is found and is more for dissimilar sequences which is verified in the simulation output. The results indicatethat real time implementation of DTW based speech recognition could be done in future.

A Skin Detection Algorithm Based on Bayes Decision in the YCbCr Color Space

2011 ◽  
Vol 121-126 ◽  
pp. 672-676 ◽  
Author(s):  
Xin Yan Cao ◽  
Hong Fei Liu
Keyword(s):  
Skin Color ◽  
Color Space ◽  
Threshold Value ◽  
Detection Algorithm ◽  
Bayesian Decision ◽  
Color Classification ◽  
Color Distribution ◽  
Ycbcr Color Space ◽  
The Face ◽  
Good Coverage

Skin color detection is a hot research of computer vision, pattern identification and human-computer interaction. Skin region is one of the most important features to detect the face and hand pictures. For detecting the skin images effectively, a skin color classification technique that employs Bayesian decision with color statistics data has been presented. In this paper, we have provided the description, comparison and evaluation results of popular methods for skin modeling and detection. A Bayesian approach to skin color classification was presented. The statistics of skin color distribution were obtained in YCbCr color space. Using the Bayes decision rule for minimum cot, the amount of false detection and false dismissal could be controlled by adjusting the threshold value. The results showed that this approach could effectively identify skin color pixels and provide good coverage of all human races, and this technique is capable of segmenting the hands and face quite effectively. The algorithm allows the flexibility of incorporating additional techniques to enhance the results.

Implementation of RGB to HSV Color Space Conversion with Xilinx System Generator

2013 ◽  
Vol 816-817 ◽  
pp. 527-534 ◽  
Author(s):  
Long Wen ◽  
Cheng Xu ◽  
Tao Li ◽  
Zheng Tian
Keyword(s):  
Color Space ◽  
Design Tool ◽  
Color Model ◽  
Hsv Color Space ◽  
System Generator ◽  
Color Space Conversion ◽  
Field Programmable ◽  
C Program ◽  
Xilinx System Generator ◽  
Program Experiment

The HSV (Hue, Saturation, and Value) color model is more intuitive than the RGB color model and widely used in color recognition and color space segmentation. Currently as the requirements of high processing speed and special applications need to realize RGB to HSV color space conversion, in this paper a new Field Programmable Gate Array (FPGA) architecture named RGB2HSV module was developed via an accurate and visible FPGA implementation method in use of Xilinx System Generator (XSG). XSG is a design tool in Simulink of MATLAB which accelerates design by providing access to highly parameterized intellectual blockset for Xilinx FPGA. In this paper simulation test images were used to measure the deviation and the time consume by the RGB2HSV module and relevant C program. Experiment shows that the maximum frequency can reach 121.433MHz and lower deviation was achieved in Xilinx Zynq xc7z020 device. The full-pipelined and parallel RGB2HSV module had been adapted in order to speed up the RGB to HSV color space conversion and took as much as 87% less than that of C program in our experiment.

Evaluation of an OpenCL-Based FPGA Platform for Particle Filter

2016 ◽  
Vol 20 (5) ◽  
pp. 743-754 ◽  
Author(s):  
Shunsuke Tatsumi ◽  
◽  
Masanori Hariyama ◽  
Norikazu Ikoma ◽  
Keyword(s):  
Particle Filter ◽  
Fpga Implementation ◽  
Design Tool ◽  
Computational Time ◽  
Major Drawback ◽  
Large Power ◽  
Internal States ◽  
Field Programmable ◽  
Power Delay Product ◽  
High Level

Particle filter is one promising method to estimate the internal states in dynamical systems, and can be used for various applications such as visual tracking and mobile-robot localization. The major drawback of particle filter is its large computational amount, which causes long computational-time and large power-consumption. In order to solve this problem, this paper proposes an Field-Programmable Gate Array (FPGA) platform for particle filter. The platform is designed using the OpenCL-based design tool that allows users to develop using a high-level programming language based on C and to change designs easily for various applications. The implementation results demonstrate the proposed FPGA implementation is 106 times faster than the CPU one, and the power-delay product of the FPGA implementation is 1.1% of the CPU one. Moreover, implementations for three different systems are shown to demonstrate flexibility of the proposed platform.

EVOLVING DECISION TREES IN HARDWARE

2009 ◽  
Vol 18 (06) ◽  
pp. 1033-1060 ◽  
Author(s):  
RASTISLAV J. R. STRUHARIK ◽  
LADISLAV A. NOVAK
Keyword(s):  
Integrated Circuits ◽  
Decision Tree ◽  
Decision Trees ◽  
Adaptive Learning ◽  
Software Evolution ◽  
Fpga Implementation ◽  
Software Implementation ◽  
Navigation Systems ◽  
Field Programmable ◽  
Tree Inference

This paper, according to the best of our knowledge, provides the very first solution to the hardware implementation of the complete decision tree inference algorithm. Evolving decision trees in hardware is motivated by a significant improvement in the evolution time compared to the time needed for software evolution and efficient use of decision trees in various embedded applications (robotic navigation systems, image processing systems, etc.), where run-time adaptive learning is of particular interest. Several architectures for the hardware evolution of single oblique or nonlinear decision trees and ensembles comprised from oblique or nonlinear decision trees are presented. Proposed architectures are suitable for the implementation using both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Results of experiments obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in inference time when compared with the traditional software implementations. In the case of single decision tree evolution, FPGA implementation of H_DTS2 architecture has on average 26 times shorter inference time when compared to the software implementation, whereas FPGA implementation of H_DTE2 architecture has on average 693 times shorter inference time than the software implementation.

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