scholarly journals An Eight-Channel Switching-Linear Hybrid Dynamic Regulator with Dual-Supply LDOs for Thermo-Optical Tuning

2021 ◽  
Author(s):  
Siyuan Zhang ◽  
min tan ◽  
Xingze Wang
Keyword(s):  
Conversion Efficiency ◽  
Small Difference ◽  
Cmos Process ◽  
Dynamic Efficiency ◽  
Efficiency Improvement ◽  
Channel Switching ◽  
Chip Area ◽  
Operating Range ◽  
Dynamic Voltage ◽  
Sinusoidal Signals

<div>A novel switching-linear hybrid dynamic regulator with dual-supply LDOs for thermo-optical tuning is presented in this brief. Compared with conventional designs, the proposed design leverages the intrinsic dual supplies to extend the operating range of the LDOs, and increases the thermo-optical tuning efficiency by reducing the dropout of the LDOs through dynamic voltage tracking. It can simultaneously regulate eight output channels and track 0.8 V<sub>pp</sub> sinusoidal waveforms at different frequencies. Significant efficiency improvement of the proposed design is achieved for envelope signals with a small difference, which is common in thermo-optical tuning. Implemented in 130 nm CMOS process, the proposed design has a total chip area of 0.675 mm<sup>2</sup>. The proposed design achieves a conversion efficiency of 88% at 1 V output driving a 200 ohms load. Its dynamic efficiency is about 80% when tracking 50 kHz sinusoidal signals.</div>

scholarly journals An Eight-Channel Switching-Linear Hybrid Dynamic Regulator with Dual-Supply LDOs for Thermo-Optical Tuning

2021 ◽  
Author(s):  
Siyuan Zhang ◽  
min tan ◽  
Xingze Wang
Keyword(s):  
Conversion Efficiency ◽  
Small Difference ◽  
Cmos Process ◽  
Dynamic Efficiency ◽  
Efficiency Improvement ◽  
Channel Switching ◽  
Chip Area ◽  
Operating Range ◽  
Dynamic Voltage ◽  
Sinusoidal Signals

<div>A novel switching-linear hybrid dynamic regulator with dual-supply LDOs for thermo-optical tuning is presented in this brief. Compared with conventional designs, the proposed design leverages the intrinsic dual supplies to extend the operating range of the LDOs, and increases the thermo-optical tuning efficiency by reducing the dropout of the LDOs through dynamic voltage tracking. It can simultaneously regulate eight output channels and track 0.8 V<sub>pp</sub> sinusoidal waveforms at different frequencies. Significant efficiency improvement of the proposed design is achieved for envelope signals with a small difference, which is common in thermo-optical tuning. Implemented in 130 nm CMOS process, the proposed design has a total chip area of 0.675 mm<sup>2</sup>. The proposed design achieves a conversion efficiency of 88% at 1 V output driving a 200 ohms load. Its dynamic efficiency is about 80% when tracking 50 kHz sinusoidal signals.</div>

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

A CMOS Temperature Sensor with a Maximum Accuracy of 1.6 °C after One-Point Calibration

2013 ◽  
Vol 336-338 ◽  
pp. 216-220
Author(s):  
Chun Chi Chen ◽  
Keng Chih Liu ◽  
Shih Hao Lin
Keyword(s):  
Temperature Sensor ◽  
Pulse Generator ◽  
Circuit Complexity ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Chip Area ◽  
Test Cost Reduction ◽  
Linear Delay ◽  
Time Amplifier ◽  
Fine Resolution

This paper presents a time-domain CMOS oscillator-based temperature sensor with one-point calibration for test cost reduction. Compared with the former CMOS sensors with linear delay lines, the proposed work composed of a temperature-to-pulse generator with adjustable time gain and a time-to-digital converter (TDC) can achieve lower circuit complexity and smaller area. A temperature-dependent oscillator for temperature sensing was used to generate the period width proportional to absolute temperature (PTAT). With the help of calibration circuit, an adjustable-gain time amplifier was adopted to dynamically adjust the amplified width that was converted by the TDC into the corresponding digital code. After calibration, the fluctuation of the sensor output with process variation can be greatly reduced. The maximum inaccuracy after one-point calibration for six package chips was 1.6 °C within a 0 80 °C temperature range. The proposed sensor fabricated in a 0.35-μm CMOS process occupied a chip area of merely 0.07 mm2, achieved a fine resolution of 0.047 °C/LSB, and consumed a low power of 25 μW@10 samples/s.

P-122: Luminous and Conversion Efficiency Improvement in OLED/OPV Tandem Device with Omnidirectional Antireflection Nanopillars

2012 ◽  
Vol 43 (1) ◽  
pp. 1516-1519 ◽  
Author(s):  
Yu-Hsuan Ho ◽  
Shun-Wei Liu ◽  
Hsun Liang ◽  
Fang-Chung Chen ◽  
Wei-Cheng Tian ◽  
...  
Keyword(s):  
Conversion Efficiency ◽  
Efficiency Improvement

scholarly journals A Highly Reliable, 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System

Sensors ◽  
2020 ◽  
Vol 20 (14) ◽  
pp. 4012 ◽  
Author(s):  
Imran Ali ◽  
Muhammad Asif ◽  
Muhammad Riaz Ur Rehman ◽  
Danial Khan ◽  
Huo Yingge ◽  
...  
Keyword(s):  
High Reliability ◽  
Digital Controller ◽  
Signal Frequency ◽  
Frequency Variation ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Chip Area ◽  
Current Consumption ◽  
Toll Collection ◽  
Complex Analog

In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high reliability and accuracy are achieved by sensing and ensuring the successive, configurable number of wake-up signal cycles before enabling power-hungry RF transceiver. The IDC and range communication (RC) oscillator current consumption is reduced by a presented self-hibernation technique during the non-wake-up period. For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated. To avoid uncertain conditions during poor and false wake-up, a watch-dog timer for IDC self-recovery is integrated. During wake-up, the digital controller consumes 34.62 nW power and draws 38.47 nA current from a 0.9 V supply. In self-hibernation mode, its current reduces to 9.7 nA. It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 µm2 area. The WuRx measured power consumption is 2.48 µW, has −46 dBm sensitivity, and a 0.484 mm² chip area.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

2.2–4.6-GHz Active Quasi-Circulator with > 24-dB Transmit–Receive Isolation

2019 ◽  
Vol 29 (05) ◽  
pp. 2050077
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Danish Kaleem ◽  
Zhi-Gong Wang ◽  
Keping Wang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
The Body ◽  
Common Source ◽  
Cmos Process ◽  
Secondary Effects ◽  
Body Effect ◽  
Chip Area ◽  
Common Gate ◽  
Loading Effects ◽  
Better Than

An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-[Formula: see text]m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of [Formula: see text] dB between transmitter-to-antenna ports ([Formula: see text]) and of [Formula: see text] dB between antenna-to-receiver ports ([Formula: see text]), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ([Formula: see text]) is better than 24 dB with a maximum value of 29.5[Formula: see text]dB @ 3.6[Formula: see text]GHz. The power dissipation of the proposed AQC is 40[Formula: see text]mW and it covers an active chip area of 0.677[Formula: see text]mm2.

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