Single Electronics for Biomedical Applications

2018 ◽  
pp. 1448-1463
Author(s):  
Deep Kamal Kaur Randhawa
Keyword(s):  
Integrated Circuits ◽  
Biomedical Applications ◽  
High Speed ◽  
Focal Point ◽  
Power Saving ◽  
Digital Signal ◽  
Signal Acquisition ◽  
Single Electronics ◽  
On Chip

The nanoelectronic circuits based on single electronics would revolutionise the new generation electronic bio-medical gadgets. The high speed nanoelectronic devices would make these gadgets faster and more accurate. The nanoelectronic integrated circuits would be a boon for power saving along with advanced portability. As the scaling down of silicon based integrated circuits is limited in nanometer regime alternative materials like organic molecules, polymers, carbon nanotubes and graphene are focal point of research. These materials exhibit various electrical, electronic and mechanical properties, flexibility being one of very significant ones. Flexible nanelectronic integrated circuits would make biomedical applications very patient friendly. The in-vivo examination and diagnosis would be less injurious to the body. Also the flexible nature will increase the maneuverability of the device by the operator. It will improve the targeted diagnosis and targeted drug delivery procedures. This would further facilitate system-on- chip (soc) that will integrate multiple biomedical signal acquisition (ECG, EEG, EP, and respiration-related signals) with on-chip digital signal processing.

Single Electronics for Biomedical Applications

2017 ◽  
pp. 212-227
Author(s):  
Deep Kamal Kaur Randhawa
Keyword(s):  
Integrated Circuits ◽  
Biomedical Applications ◽  
High Speed ◽  
Focal Point ◽  
Power Saving ◽  
Digital Signal ◽  
Signal Acquisition ◽  
Single Electronics ◽  
On Chip

The nanoelectronic circuits based on single electronics would revolutionise the new generation electronic bio-medical gadgets. The high speed nanoelectronic devices would make these gadgets faster and more accurate. The nanoelectronic integrated circuits would be a boon for power saving along with advanced portability. As the scaling down of silicon based integrated circuits is limited in nanometer regime alternative materials like organic molecules, polymers, carbon nanotubes and graphene are focal point of research. These materials exhibit various electrical, electronic and mechanical properties, flexibility being one of very significant ones. Flexible nanelectronic integrated circuits would make biomedical applications very patient friendly. The in-vivo examination and diagnosis would be less injurious to the body. Also the flexible nature will increase the maneuverability of the device by the operator. It will improve the targeted diagnosis and targeted drug delivery procedures. This would further facilitate system-on- chip (soc) that will integrate multiple biomedical signal acquisition (ECG, EEG, EP, and respiration-related signals) with on-chip digital signal processing.

Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

PC104 Interface Recommended for High Speed Data Acquisition Systems

2013 ◽  
Vol 325-326 ◽  
pp. 926-929 ◽  
Author(s):  
Dorina Purcaru ◽  
Cornelia Gordan ◽  
Romulus Reiz ◽  
Anca Purcaru
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Low Cost ◽  
Sampling Rate ◽  
Digital Signal ◽  
Signal Acquisition ◽  
Synchronized Sampling ◽  
Data Acquisition Systems ◽  
High Speed Data Acquisition ◽  
High Speed Data

The interface presented in this paper is recommended for high speed data acquisition systems; it performs a synchronized sampling of all common-mode or differential analog inputs with a high sampling rate. This is a low cost interface, entirely controlled by the PC104 CPU. Programmable electronic modules that contain such PC104 interfaces can be found running in the energetic system from Romania; these dedicated equipments perform the analog and digital signal acquisition for monitoring and recording different specific transient events. Some experimental results obtained using the disturbance monitoring device PC-08/104 are also presented in this paper.

scholarly journals Design and Analysis of Low Power SRAM using CMOS Technology

2019 ◽  
Vol 8 (12S) ◽  
pp. 896-902
Keyword(s):  
Integrated Circuits ◽  
Power Saving ◽  
Cmos Technology ◽  
Video Data ◽  
Compression Technique ◽  
Spatial Locality ◽  
Temporal And Spatial ◽  
On Chip ◽  
Technology Nodes ◽  
Application Specific

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings..

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

2018 ◽  
Vol 57 (4) ◽  
pp. 361-375 ◽  
Author(s):  
J Jency Rubia ◽  
GA Sathish Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Large Scale ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Hardware Complexity ◽  
Logarithmic Number System ◽  
Logarithmic Number

The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment.

Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits

2015 ◽  
Vol 25 (03) ◽  
pp. 1640014
Author(s):  
Florence Azaïs ◽  
Stéphane David-Grignot ◽  
Laurent Latorre ◽  
François Lefevre
Keyword(s):  
Integrated Circuits ◽  
Phase Noise ◽  
Digital Signature ◽  
Signal Acquisition ◽  
Rf Integrated Circuits ◽  
Embedded Test ◽  
Silicon Area ◽  
Test Instrument ◽  
On Chip ◽  
Minimal Hardware

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140[Formula: see text]nm technology occupies only 7,885[Formula: see text][Formula: see text]m2, which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

scholarly journals Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

1992 ◽  
Vol 14 (4) ◽  
pp. 199-218 ◽  
Author(s):  
K. Z. Dimopoulos ◽  
J. N. Avaritsiotis ◽  
S. J. White
Keyword(s):  
Integrated Circuits ◽  
Transmission Lines ◽  
High Speed ◽  
Pulse Propagation ◽  
Unit Length ◽  
Coupled Line ◽  
Lossy Transmission ◽  
Electrical Modelling ◽  
High Bit Rates ◽  
On Chip

A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.

scholarly journals An Area Efficient Wallace Tree Multiplier using Modified Full Adder

2020 ◽  
Vol 8 (6) ◽  
pp. 3383-3386
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Nand Gate ◽  
Silicon Area ◽  
Wallace Tree ◽  
Multiplication Process ◽  
Wallace Tree Multiplier ◽  
Area Efficient

Multipliers play a significant task in digital signal processing applications and application-specific integrated circuits. Wallace tree multipliers provide a high-speed multiplication process with an area-efficient strategy. It is realized in hardware using full adders and half adders. The optimization of adders can further improve the performance of multipliers. Wallace tree multiplier with modified full adder using NAND gate is proposed to achieve reduced silicon area, high speed and low power consumption. The conventional full adder implemented by XOR, AND, OR gates is replaced by the modified full adder realized using NAND gate. The proposed Wallace tree multiplier includes 544 transistors, while the conventional Wallace tree multiplier has 584 transistors for 4-bit multiplication.

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