Ultra-Low-Power Strategy for Reliable IoE Nanoscale Integrated Circuits

2019 ◽  
pp. 246-271 ◽  
Author(s):  
Jorge Semião ◽  
Ruben Cabral ◽  
Hugo Cavalaria ◽  
Marcelino Santos ◽  
Isabel C. Teixeira ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Cmos Technology ◽  
Battery Life ◽  
Portable Devices ◽  
Transient Faults ◽  
Ultra Low Power ◽  
Power Strategies ◽  
Dynamic Voltage ◽  
Subthreshold Voltage

Ultra-low-power strategies have a huge importance in today's integrated circuits designed for internet of everything (IoE) applications, as all portable devices quest for the never-ending battery life. Dynamic voltage and frequency scaling techniques can be rewarding, and the drastic power savings obtained in subthreshold voltage operation makes this an important technique to be used in battery-operated devices. However, unpredictability in nanoscale chips is high, and working at reduced supply voltages makes circuits more vulnerable to operational-induced delay-faults and transient-faults. The goal is to implement an adaptive voltage scaling (AVS) strategy, which can work at subthreshold voltages to considerably reduce power consumption. The proposed strategy uses aging-aware local and global performance sensors to enhance reliability and fault-tolerance and allows circuits to be dynamically optimized during their lifetime while prevents error occurrence. Spice simulations in 65nm CMOS technology demonstrate the results.

scholarly journals Rural Healthcare IoT Architecture Based on Low-Energy LoRa

2021 ◽  
Vol 18 (14) ◽  
pp. 7660
Author(s):  
Ace Dimitrievski ◽  
Sonja Filiposka ◽  
Francisco José Melero ◽  
Eftim Zdravevski ◽  
Petre Lameski ◽  
...  
Keyword(s):  
Low Power ◽  
Rural Areas ◽  
Urban Areas ◽  
Well Being ◽  
Battery Life ◽  
Ultra Low Power ◽  
Term Operation ◽  
Doctor Patient Communication ◽  
Connected Health ◽  
Iot Devices

Connected health is expected to introduce an improvement in providing healthcare and doctor-patient communication while at the same time reducing cost. Connected health would introduce an even more significant gap between healthcare quality for urban areas with physical proximity and better communication to providers and the portion of rural areas with numerous connectivity issues. We identify these challenges using user scenarios and propose LoRa based architecture for addressing these challenges. We focus on the energy management of battery-powered, affordable IoT devices for long-term operation, providing important information about the care receivers’ well-being. Using an external ultra-low-power timer, we extended the battery life in the order of tens of times, compared to relying on low power modes of the microcontroller.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

Ultra low power: Emerging devices and their benefits for integrated circuits

2011 ◽  
Author(s):  
Adrian M. Ionescu ◽  
Luca De Michielis ◽  
Nilay Dagtekin ◽  
Giovanni Salvatore ◽  
Ji Cao ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Ultra Low Power

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

Sign in / Sign up

Export Citation Format

Share Document