A Capacitive Humidity Sensor for Low-Cost Low-Power Application

2014 ◽  
Vol 556-562 ◽  
pp. 1847-1851
Author(s):  
Xiang Wu ◽  
Fang Ming Deng
Keyword(s):  
Humidity Sensor ◽  
Supply Voltage ◽  
Low Cost ◽  
Cmos Technology ◽  
Cmos Process ◽  
Sensor Interface ◽  
Interface Circuit ◽  
Digital Architecture ◽  
Power Application ◽  
Capacitive Humidity Sensor

This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface employs a fully-digital architecture based on phase locked loop, which results in low pow dissipation. The proposed humidity sensor is fabricated in TSMC 0.18μm CMOS process and the chip occupies an area of 0.05mm2. The measurement result shows that the sensor value exhibits good linearity within the range of 10-90%RH and the interface circuit consumes only 1.05μW at 0.5V supply voltage.

A Low-Cost Low-Power Capacitive Humidity Sensor in CMOS Technology

2014 ◽  
Vol 556-562 ◽  
pp. 1842-1846
Author(s):  
Fang Ming Deng ◽  
Yi Gang He
Keyword(s):  
Humidity Sensor ◽  
Supply Voltage ◽  
Low Cost ◽  
Cmos Technology ◽  
Cmos Process ◽  
Sensing Element ◽  
Digital Conversion ◽  
Sensor Interface ◽  
Delta Sigma ◽  
Capacitive Humidity Sensor

This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface is based on a delta-sigma converter and can be easily reconfigured to compensate for process variation of the sensing element. The proposed humidity sensor is fabricated in 0.16μm standard CMOS process and the chip occupies 0.25mm2. The measurement result shows that this humidity sensor acquires a resolution of 0.1%RH in the range of 20%RH to 90%RH. The interface achieves a 12.5-bits capacitance-to-digital conversion and consumes only 9.6μW power at 1.2V supply voltage.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

Capacitive humidity sensor in CMOS technology

2001 ◽  
Author(s):  
Xian-Wei Yan ◽  
Ming Qin ◽  
Qing-An Huang
Keyword(s):  
Humidity Sensor ◽  
Cmos Technology ◽  
Capacitive Humidity Sensor

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

A CCII-Based Oscillating Circuit as Resistive/Capacitive Humidity Sensor Interface

2011 ◽  
pp. 293-299
Author(s):  
Andrea De Marcellis ◽  
Claudia Di Carlo ◽  
Giuseppe Ferri ◽  
Carlo Cantalini ◽  
Luca Giancaterini
Keyword(s):  
Humidity Sensor ◽  
Sensor Interface ◽  
Capacitive Humidity Sensor

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

Design of Conductive MWNTs/SiO2 Humidity Sensor Interface ASIC Based on AC Signals

2013 ◽  
Vol 562-565 ◽  
pp. 344-349
Author(s):  
Tuo Li ◽  
Xiao Wei Liu ◽  
Liang Yin ◽  
Chang Chun Dong
Keyword(s):  
Humidity Sensor ◽  
Work Group ◽  
High Sensitivity ◽  
Cmos Process ◽  
Humidity Sensing ◽  
Interface Circuit ◽  
Testing Frequency ◽  
Zero Offset ◽  
Different Response ◽  
Circuit Output

Previous research on MWNTs/SiO2 humidity sensing film by our work group has proved that MWNTs sensor has a different response mechanism to humidity at AC testing signals and shows greater testing stability and higher sensitivity, compared with traditional DC signal measurement. An interface circuit for conductive MWNTs/SiO2 humidity sensor is designed in this paper for humidity detection and prospection in miniaturization and integration. It aims at detecting the sensor’s humidity sensitive conductance signal at AC testing signals, and inhibiting the interference of capacitance signals. The ASIC demodulates the two signals by their phase difference and outputs a direct voltage proportional to conductance. The layout for ASIC is drawn by standard 0.5um P2M2 CMOS process and has a total area of 4*2mm2. In circuit level simulation by HSPICE which introduces practical data of the sensor’s humidity sensing characteristics, the relation of circuit output to conductance turns out to have great linearity at no more than 300 kHz and zero offset can be neglected at less than 100 kHz frequency. It is feasible to select proper testing frequency for high sensitivity and stability and make further investigations on the sensor’s frequency property.

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