Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

A LOW-POWER UWB TRANSCEIVER BY USE OF TRIGGER RECEIVING METHOD

2010 ◽  
Vol 19 (07) ◽  
pp. 1609-1619 ◽  
Author(s):  
SHENG ZHANG ◽  
ZHENG LI ◽  
MENGMENG LIU ◽  
XIAOKANG LIN
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Circuit Complexity ◽  
Cmos Process ◽  
Fully Integrated

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm2 and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

CMOS Low Power Ring VCO Design

2014 ◽  
Vol 981 ◽  
pp. 70-73
Author(s):  
Ming Xin Song ◽  
Shan Shan Wang ◽  
Guo Dong Sun
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Simple Structure ◽  
Low Voltage ◽  
Central Component ◽  
Voltage Controlled Oscillator ◽  
Frequency Range ◽  
Central Frequency ◽  
Small Phase ◽  
Voltage Phase

A design project of voltage controlled oscillator which is the central component of the low voltage phase locked loop (PLL) is proposed in this paper. The VCO adopted the folding differential voltage controlled oscillator.Simulation results in Cadence Hspice indicate that the VCO proposed behaves in good linearity, simple structure, small phase noise.The frequency range from 125 to 787 MHz, the power consumption of this oscillator is only 6mW at central frequency is 480MHz with 3V power supply.

TUNABLE ACTIVE FILTERS FOR RF AND MICROWAVE APPLICATIONS

2014 ◽  
Vol 23 (06) ◽  
pp. 1450088 ◽  
Author(s):  
LEONARDO PANTOLI ◽  
VINCENZO STORNELLI ◽  
GIORGIO LEUZZI
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Bandpass Filter ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Active Filters ◽  
Center Frequency ◽  
Power Supply Voltage ◽  
Microwave Applications

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

Design of Micro Power Consumption Synchronous Chopped Wave Power Supply Based on Fixed and Mobile Double Comparative Point

2014 ◽  
Vol 986-987 ◽  
pp. 1794-1798
Author(s):  
Long Teng Wang ◽  
Jun Lin ◽  
Hui Su
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Output Voltage ◽  
Low Voltage ◽  
Design Method ◽  
Short Circuit ◽  
Maximum Output ◽  
Residual Voltage ◽  
Micro Power

This paper proposes a design method of the micro power consumption synchronous chopped wave and low-power switching power supply based on fixed and mobile double comparative point. The output of this power supply ranges from 5V to 200V. It overcomes the residual voltage effect after the bridge rectifier by using fixed comparative point to limit the maximum output voltage, and stabilizes the voltage by using mobile point to produce the required output voltage. The circuit charges with nonlinear resistors pattern in the low voltage, thus improving the charging efficiency, and it has short circuit protection function, simple structure and low power consumption.

Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply

2019 ◽  
Vol 15 (3) ◽  
pp. 323-328
Author(s):  
José C. García ◽  
Juan A. Montiel-Nelson ◽  
Saeid Nooshabadi
Keyword(s):  
Low Voltage ◽  
Propagation Delay ◽  
Current Conveyor ◽  
Superior Performance ◽  
Cmos Process ◽  
Resistive Load ◽  
Process Technology ◽  
Digital Vlsi ◽  
Input Signals ◽  
Target Design

A low voltage supply CMOS current conveyor circuit for digital input signals from 0.25 V up to 1.2 V is presented. The circuit is optimized and pre-layout simulated in a 65 nm CMOS process technology. At the target design voltage of 1.2 V, the current conveyor has a propagation delay of 2.86 ns, an energy consumption of only 80.9 pJ, and energy-delay product (EDP) of 231 pJns for resistive load of 10 kΩ. Superior performance of this work is demonstrated through comparison with other similar published work at a frequency of 5 MHz. It is shown that the proposed circuit is suitable for digital signaling. The developed CMOS circuit perfoms correctly until 50 MHz and its EDP is 31 pJns at 10 kΩ.

scholarly journals 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1383
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Gaetano Palumbo
Keyword(s):  
Power Consumption ◽  
Low Voltage ◽  
Building Blocks ◽  
Frequency Divider ◽  
Cmos Process ◽  
Design Strategies ◽  
Frequency Dividers ◽  
Level Shifter ◽  
Forward Body Bias ◽  
Body Bias

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques

2018 ◽  
Vol 27 (07) ◽  
pp. 1850111 ◽  
Author(s):  
J. J. Ocampo-Hidalgo ◽  
J. Alducín-Castillo ◽  
I. Vázquez-Álvarez ◽  
L. N. Oliva-Moreno ◽  
J. E. Molinar-Solís
Keyword(s):  
High Resistance ◽  
Small Area ◽  
Low Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Process Models ◽  
Cmos Process ◽  
Gain Bandwidth ◽  
Measurement Results ◽  
Improved Performance

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

Sign in / Sign up

Export Citation Format

Share Document