Effect of Phosphorus Implantation Prior to Oxidation on Electrical Properties of Thermally Grown SiO2/4H-SiC MOS Structures

2014 ◽  
Vol 806 ◽  
pp. 133-138 ◽  
Author(s):  
Aleksey Mikhaylov ◽  
Tomasz Sledziewski ◽  
Alexey Afanasyev ◽  
Victor Luchinin ◽  
Sergey A. Reshanov ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Reference Sample ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Phosphorus Concentration ◽  
Interface Traps ◽  
Mos Capacitor ◽  
Mos Devices ◽  
Dry Oxidation ◽  
Mos Structures

The electrical properties of metal-oxide-semiconductor (MOS) devices fabricated using dry oxidation on phosphorus-implanted n-type 4H-SiC (0001) epilayers have been investigated. MOS structures were compared in terms of interface traps and reliability with reference sample which was produced by dry oxidation under the same conditions. The notably lower interface traps density measured in MOS capacitor with phosphorus concentration exceeding 1018 cm-3 at the SiO2/SiC interface was attributed to interface traps passivation by incorporated phosphorus ions.

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

Electrical Properties of Metal-Oxide-Semiconductor (MOS) Structures on 4H-SiC(0001) Formed by Oxidizing Pre-Deposited SixNy

2007 ◽  
Vol 556-557 ◽  
pp. 647-650 ◽  
Author(s):  
Jeong Hyun Moon ◽  
Dong Hwan Kim ◽  
Ho Keun Song ◽  
Jeong Hyuk Yim ◽  
Wook Bahng ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Metal Oxide ◽  
Current Density ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Field ◽  
Mos Capacitors ◽  
Dielectric Layers ◽  
Capacitance Voltage ◽  
Mos Structures

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with ultra thin (5 nm) remote-PECVD SixNy dielectric layers and investigated electrical properties of nitrided SiO2/4H-SiC interface after oxidizing the SixNy in dry oxygen at 1150 °C for 30, 60, 90 min. Improvements of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements in comparison with dry oxide. The improvements of SiC MOS capacitors formed by oxidizing the pre-deposited SixNy have been explained in this paper.

Charge Trap Mechanism in Hybrid Nanostructured (YMnO3) Metal-Oxide-Semiconductor (MOS) Devices

2016 ◽  
Vol 42 ◽  
pp. 92-99
Author(s):  
J.H. Markna ◽  
Davit Dhruv ◽  
K.N. Rathod ◽  
Chirag Savaliya ◽  
T.M. Shiyani ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Oxide Layer ◽  
Debye Length ◽  
Anomalous Behavior ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mos Capacitor ◽  
Charge Trap ◽  
Mos Devices ◽  
A Charge

Hybrid nanostructured Metal Oxide Semiconductor (MOS) capacitor was fabricated on silicon substrates (n-type) using chemical solution deposition with YMnO3 as an oxide layer. Electrical properties of MOS capacitor have been investigated with frequency dependence capacitance-voltage (C-V) characterization. The surface morphology of deposited layer was studied using the Atomic Force Microscopy (AFM). Hysteresis in the C-V loop and change in the values of Cminimum were described by a charge trap mechanism in the multiferroic oxide layer of MOS devices. While anomalous behavior in saturation capacitance in the inversion as well as in accumulation region and a shift in threshold voltage (VT) were explained in the vicinity of frequency depended Debye length (LDebye).

scholarly journals Interface chemistry and leakage current mechanism of HfGdON/Ge gate stack modulated by ALD-driven interlayer

RSC Advances ◽  
2019 ◽  
Vol 9 (58) ◽  
pp. 33800-33805
Author(s):  
Gang He ◽  
Die Wang ◽  
Rui Ma ◽  
Mao Liu ◽  
Jingbiao Cui
Keyword(s):  
Electrical Properties ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Stacks ◽  
Interface Chemistry ◽  
Mos Capacitor ◽  
Passivation Treatment ◽  
Leakage Current Mechanism ◽  
Current Mechanism

In the current manuscript, a Ge metal-oxide-semiconductor (MOS) capacitor based on HfGdON/Ge gate stacks with an ALD-driven passivation layer has been fabricated, and its interfacial and electrical properties are compared with those of its counterparts that have not undergone passivation treatment.

scholarly journals A method for characterizing near-interface traps in SiC metal–oxide–semiconductor capacitors from conductance–temperature spectroscopy measurements

2021 ◽  
Vol 129 (5) ◽  
pp. 054501
Author(s):  
Jordan R. Nicholls ◽  
Arnar M. Vidarsson ◽  
Daniel Haasmann ◽  
Einar Ö. Sveinbjörnsson ◽  
Sima Dimitrijev
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps
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