Advances in Fast Epitaxial Growth of 4H-SiC and Defect Reduction

2016 ◽  
Vol 858 ◽  
pp. 119-124 ◽  
Author(s):  
Hidekazu Tsuchida ◽  
Isaho Kamata ◽  
Masahiko Ito ◽  
Tetsuya Miyazawa ◽  
Hideyuki Uehigashi ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
High Throughput ◽  
Growth Rates ◽  
High Speed ◽  
Stacking Faults ◽  
High Quality ◽  
Defect Reduction ◽  
Induced Defects ◽  
Defect Densities ◽  
Gas Supply

This paper reports on recent advances in 4H-SiC epitaxial growth toward high-throughput production of high-quality and uniform 150 mm-diameter 4H-SiC epilayers by enhancing of growth rates, improving uniformity and reducing defect densities. A vertical single-wafer type SiC epitaxial reactor is employed and high-speed wafer rotation is confirmed as effective, not only for enhancing growth rates without increasing the source gas supply but also improving thickness and doping uniformities. The current levels of reducing particle-induced defects, in-grown stacking faults, basal plane dislocations and the Z1/2 center (carbon vacancies) are reviewed.

Lateral growth of AlxGa1–xN and GaN on SiC substrates patterned by photo-electrochemical etching

2002 ◽  
Vol 743 ◽  
Author(s):  
U. Rossów ◽  
N. Riedel ◽  
F. Hitzel ◽  
T. Riedl ◽  
A. Hangleiter
Keyword(s):  
Growth Rates ◽  
Electrochemical Etching ◽  
Layered Structures ◽  
Lateral Growth ◽  
Large Defect ◽  
Defect Reduction ◽  
Group Iii ◽  
Group Iii Nitride ◽  
Nitride Layers ◽  
Defect Densities

AbstractThe large defect densities in heteroepitaxially grown group-III-nitride layers on sapphire or SiC cannot be tolerated in applications such as lasers. We report here on a defect reduction by overgrowth of patterned n-6H-SiC(0001)surfaces.First, we formed mesa structures in the windows of metal masks and then after removal of the masks layers of AlxGa1–xN and GaN were grown by low-pressure MOVPE under conditions of high lateral growth rates. We demonstrate that layers and layered structures can be grown with smooth surfaces and reduced defect densities.

Triangular Defects Reduction and Uniformity Improvement of 4H-SiC Epitaxial Growth in a Planetary Reactor

2018 ◽  
Vol 924 ◽  
pp. 104-107
Author(s):  
Wei Li Lu ◽  
Jia Li ◽  
Yu Long Fang ◽  
Jia Yun Yin ◽  
Zhi Hong Feng
Keyword(s):  
Epitaxial Growth ◽  
Leakage Current ◽  
High Throughput ◽  
High Voltage ◽  
High Performance ◽  
Etching Process ◽  
Power Devices ◽  
High Quality ◽  
Recent Advances

High quality SiC Epilayers are essential for the development of high performance power devices. Killer defects such as triangular defects could cause leakage current paths within the high voltage SiC devices. This paper reports on the recent advances in 4H-SiC epitaxial growth toward high-throughput production in a commercial planetary reactor. The triangular defects are suppressed by the optimized pre-etching process, and the physics behind was investigated. The doping and thickness uniformities of the intra-wafer and wafer-to-wafer have also been improved.

SiC Epitaxial Growth on Multiple 100-mm Wafers and its Application to Power-Switching Devices

2008 ◽  
Vol 600-603 ◽  
pp. 77-82 ◽  
Author(s):  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
Joseph J. Sumakeris ◽  
C. Hallin ◽  
Elif Berkman ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Vapor Phase ◽  
High Throughput ◽  
Low Cost ◽  
Wide Bandgap ◽  
High Quality ◽  
Power Switching ◽  
Recent Emergence ◽  
Switching Devices

The development of SiC bulk and epitaxial materials is reviewed with an emphasis on epitaxial growth using high-throughput, multi-wafer, vapor phase epitaxial (VPE) warm-wall planetary reactors. It will be shown how the recent emergence of low-cost high-quality 100-mm diameter epitaxial SiC wafers is enabling the economical production of advanced wide-bandgap Power–Switching devices.

Defect Status in SiC Manufacturing

2009 ◽  
Vol 615-617 ◽  
pp. 3-6 ◽  
Author(s):  
Elif Berkman ◽  
R.T. Leonard ◽  
Michael J. Paisley ◽  
Y. Khlebnikov ◽  
Michael J. O'Loughlin ◽  
...  
Keyword(s):  
Large Diameter ◽  
Commercial Application ◽  
Optical Surface ◽  
High Quality ◽  
Successful Development ◽  
X Ray ◽  
Selective Etch ◽  
Induced Defects ◽  
Defect Densities ◽  
Optical Surface Analyzer

Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

scholarly journals Characterization of the Dip Pen Nanolithography Process for Nanomanufacturing

2011 ◽  
Vol 133 (4) ◽  
Author(s):  
Sourabh K. Saha ◽  
Martin L. Culpepper
Keyword(s):  
Tool Life ◽  
High Throughput ◽  
High Speed ◽  
High Quality ◽  
Processing Rate ◽  
Process Modification ◽  
Process System ◽  
Nanoscale Features ◽  
Dip Pen Nanolithography

Dip pen nanolithography (DPN) is a flexible nanofabrication process for creating 2-D nanoscale features on a surface using an “inked” tip. Although a variety of ink-surface combinations can be used for creating 2-D nanofeatures using DPN, the process has not yet been characterized for high throughput and high quality manufacturing. Therefore, at present it is not possible to (i) predict whether fabricating a part is feasible within the constraints of the desired rate and quality and (ii) select/design equipment appropriate for the desired manufacturing goals. Herein, we have quantified the processing rate, tool life, and feature quality for DPN line writing by linking these manufacturing metrics to the process/system parameters. Based on this characterization, we found that (i) due to theoretical and practical constraints of current technology, the processing rate cannot be increased beyond about 20 times the typical rate of ∼1 μm2/min, (ii) tool life for accurate line writing is limited to 1–5 min, and (iii) sensitivity of line width to process parameters decreases with an increase in the writing speed. Thus, we conclude that for a high throughput and high quality system, we need (i) parallelization or process modification to improve throughput and (ii) accurate fixtures for rapid tool change. We also conclude that process control at high speed writing is less stringent than at low speed writing, thereby suggesting that DPN has a niche in high speed writing of narrow lines.

scholarly journals Stacking Faults Defects on 3C-SiC Homo-Epitaxial Films

2018 ◽  
Vol 924 ◽  
pp. 124-127 ◽  
Author(s):  
Grazia Litrico ◽  
Ruggero Anzalone ◽  
Alessandra Alberti ◽  
Corrado Bongiorno ◽  
Giuseppe Nicotra ◽  
...  
Keyword(s):  
High Resolution ◽  
Epitaxial Growth ◽  
Growth Condition ◽  
Stacking Faults ◽  
Epitaxial Films ◽  
Stem Analysis ◽  
High Quality ◽  
Main Defect ◽  
Quality Material

Stacking Faults (SFs) are the main defect of 3C-SiC material and in this work a detailed study of this typology of defect is presented. We studied the behavior of SFs with High Resolution XRD and STEM analysis. The homo-epitaxial growth was proposed as a solution for the reduction of SFs density in 3C-SiC material and the influence of the growth condition on the SFs density was studied. The knowledge of the mechanism of SFs reduction is crucial for the development of a high quality material for devices fabrication.

Fast 4H-SiC Epitaxial Growth on 150 mm Diameter Area with High-Speed Wafer Rotation

2014 ◽  
Vol 778-780 ◽  
pp. 117-120 ◽  
Author(s):  
Hiroaki Fujibayashi ◽  
Masahiko Ito ◽  
Hideki Ito ◽  
Isaho Kamata ◽  
Masami Naitou ◽  
...  
Keyword(s):  
Growth Rate ◽  
Epitaxial Growth ◽  
Growth Rates ◽  
High Speed ◽  
Smooth Surface ◽  
Doping Concentration ◽  
Defect Density ◽  
High Growth ◽  
High Growth Rate ◽  
Step Bunching

A single wafer type 150 mm vertical 4H-SiC epitaxial reactor with high-speed wafer rotation was developed. The rotation of the wafer at high speed significantly enhances the growth rate, and high growth rates of 40–50 μm/h are possible on 4°off-cut 4H-SiC substrates. In addition, a low defect density and smooth surface without macro step bunching can be achieved. Excellent uniformity of thickness and doping concentration was obtained for a 150 mm wafer at a high growth rate of 50 μm/h.

Evolution of Fast 4H-SiC CVD Growth and Defect Reduction Techniques

2014 ◽  
Vol 778-780 ◽  
pp. 85-90 ◽  
Author(s):  
Hidekazu Tsuchida ◽  
Isaho Kamata ◽  
Masahiko Ito ◽  
Tetsuya Miyazawa ◽  
Norihiro Hoshino ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
High Speed ◽  
Gas Flow ◽  
Threading Dislocations ◽  
Defect Reduction ◽  
Bulk Growth ◽  
Reduction Techniques ◽  
Gas Source ◽  
Cvd Growth ◽  
Gas Flow Velocity

This paper introduces our recent challenges in fast 4H-SiC CVD growth and defect reduction. Enhanced growth rates in 4H-SiC epitaxial growth by high-speed wafer rotation and in a high-temperature gas source method promoting SiC bulk growth by increasing the gas flow velocity are demonstrated. Trials and results of deflecting threading dislocations by patterned C-face 4H-SiC epitaxial growth are also shown.

Quantitative defect studies in semiconductor TEM samples prepared by low angle ion milling

1995 ◽  
Vol 53 ◽  
pp. 512-513
Author(s):  
L. Mulestagno ◽  
J.C. Holzer ◽  
P. Fraundorf
Keyword(s):  
Sample Preparation ◽  
Milling Time ◽  
High Density ◽  
Low Density ◽  
Ion Milling ◽  
High Quality ◽  
Variable Angle ◽  
Major Disadvantage ◽  
Induced Defects

Due to the wealth of information, both analytical and structural that can be obtained from it TEM always has been a favorite tool for the analysis of process-induced defects in semiconductor wafers. The only major disadvantage has always been, that the volume under study in the TEM is relatively small, making it difficult to locate low density defects, and sample preparation is a somewhat lengthy procedure. This problem has been somewhat alleviated by the availability of efficient low angle milling.Using a PIPS® variable angle ion -mill, manufactured by Gatan, we have been consistently obtaining planar specimens with a high quality thin area in excess of 5 × 104 μm2 in about half an hour (milling time), which has made it possible to locate defects at lower densities, or, for defects of relatively high density, obtain information which is statistically more significant (table 1).

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

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