Improvement of SiO2/4H-SiC Interface Quality by Post-Oxidation Annealing in N2 at High-Temperatures

2016 ◽  
Vol 858 ◽  
pp. 627-630 ◽  
Author(s):  
Atthawut Chanthaphan ◽  
Yen Hung Cheng ◽  
Takuji Hosoi ◽  
Takayoshi Shimura ◽  
Heiji Watanabe
Keyword(s):  
Photoelectron Spectroscopy ◽  
Annealing Temperature ◽  
Electrical Characterization ◽  
Practical Method ◽  
Interface State ◽  
State Density ◽  
Interface Quality ◽  
Mos Capacitors ◽  
X Ray ◽  
Mos Devices

The efficient and practical method for SiO2/4H-SiC interface improvement using post-oxidation annealing (POA) in pure N2 ambient was studied by means of x-ray photoelectron spectroscopy (XPS) analysis and electrical characterization. SiC-MOS capacitors with slope-shaped thermal oxides were used to investigate optimal conditions for interface nitridation. It was found that the amount of nitrogen atoms incorporated into the interfaces increased when raised the annealing temperature up to 1400°C, and thin oxide (< 30 nm) was used. Furthermore, N2-POA at 1400°C was proven to be very promising as equivalent to NO-POA in terms of reduced interface state density of SiC-MOS devices.

Investigation of Interface State Density with Varied SiO2 Thickness in La2O3/SiO2/4H-SiC MOS Capacitors

2016 ◽  
Vol 858 ◽  
pp. 689-692 ◽  
Author(s):  
Yu Cheng Wang ◽  
Yu Ming Zhang ◽  
Ren Xu Jia
Keyword(s):  
Photoelectron Spectroscopy ◽  
Lattice Mismatch ◽  
Atomic Layer ◽  
Interface State ◽  
Carbon Cluster ◽  
State Density ◽  
Oxide Semiconductor ◽  
Interface Quality ◽  
Mos Capacitors ◽  
Layer Deposition

SiO2 with varying thickness (0, 4.45, and 8.05 nm) were grown on n type 4H-SiC epilayer by thermal oxidation and La2O3 were stacked on them using atomic layer deposition (ALD). The La2O3/SiO2/4H-SiC metal-oxide-semiconductor (MOS) capacitors were analyzed by X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) measurements. C-V curves show that introducing an ultrathin SiO2 can reduce the effect of lattice mismatch of La2O3/4H-SiC structure and then improve interface property. However, the interface quality is reduced as SiO2 was grown thicker. XPS data show that more carbon cluster remains at the interfacial between SiO2 and 4H-SiC as the oxidation time increases.

Characterizations of Ultra-thin Dielectrics Grown by Microwave Afterglow O2/N2O Plasma Oxidation at Low Temperature with Rapid Thermal Annealing

1995 ◽  
Vol 387 ◽  
Author(s):  
Po-ching Chen ◽  
Klaus Yung-jane Hsu ◽  
Joseph J. Loferski ◽  
Huey-liang Hwang
Keyword(s):  
Low Temperature ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Photoelectron Spectroscopy ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Plasma Oxidation ◽  
X Ray ◽  
Thin Dielectrics

AbstractMicrowave afterglow plasma oxidation at a low temperature (600 °C ) and rapid thermal annealing (RTA) were combined to grow high quality ultra-thin dielectrics. This new approach has a low thermal budget. The mid-gap interface state density of oxides pretreated in N2O plasma was decreased to about 5×1010 cm−2eV−1 after rapid thermal annealing at 950 °C.It was found that RTA is very effective for relieving the oxide stress and reducing the interface state density. Nitrogen incorporated in oxides by the N2O plasma pretreatment of the Si surface helped to reduce the interface state density. Microstructures of ultra-thin oxide grown by microwave afterglow oxidation with or without RTA were revealed by extended-X-ray-absorption-finestructure (EXAFS) and X-ray photoelectron spectroscopy (XPS) analysis.

Effect of Interfacial Localization of Phosphorus on Electrical Properties and Reliability of 4H-SiC MOS Devices

2013 ◽  
Vol 740-742 ◽  
pp. 695-698 ◽  
Author(s):  
Tsuyoshi Akagi ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Device Properties ◽  
Phosphorus Doped ◽  
Post Deposition ◽  
Mos Device

Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO2/SiC interface were fabricated on 4H-SiC by direct POCl3treatment followed by SiO2deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

Characterization of Rapid Nitrided Ultrathin SiO2 Films By XPS and SCS

1995 ◽  
Vol 387 ◽  
Author(s):  
H. Yan ◽  
S. P. Wong ◽  
R. W. M. Chan ◽  
R. W. M. Kwok ◽  
W. X. Feng
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interface State ◽  
Dielectric Surface ◽  
State Density ◽  
Breakdown Field ◽  
Silicon Substrates ◽  
X Ray ◽  
Dielectric Layers ◽  
Breakdown Field Strength

AbstractUltrathin SiO2 dielectric layers of thickness less than 100Å on silicon substrates have been prepared by dry oxidation and rapid thermal nitirdation (RTN). In this study, X-ray photoelectron spectroscopy and surface charge spectroscopy had been applied to study the nitrogen distribution in the dielectric layers and the change in the interface state density (Dit) due to the nitrogen incorporation. It is found that most of the incorporated nitrogen is located near the dielectric/Si interface and the nitrogen content increases with the RTN temperature. For the electrical properties, we found that the Dit, after RTN slightly decreases and the breakdown field strength deduced from the dielectric surface potential was enhanced by the incorporation of nitrogen.

Significant Decrease of the Interface State Density by NH3 Plasma Pretreatment at 4H-SiC (000-1) Surface and its Bond Configuration

2010 ◽  
Vol 645-648 ◽  
pp. 503-506 ◽  
Author(s):  
Yoshinori Iwasaki ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Interface Properties ◽  
Dangling Bonds ◽  
X Ray ◽  
Plasma Pretreatment

We have investigated NH3 plasma pretreatment for Si- and C-face 4H-SiC and characterized interface properties and bond configuration. It is revealed that the NH3 plasma pretreatment is effective to reduce interface state density on C-face. From X-ray photoelectron spectroscopy (XPS) measurements, N- and H-related C bonds were observed. N and H passivate C-related defects and dangling bonds, resulting in improved interface properties.

Fabrication and Characterization of 4H-SiC MOSFET with MOCVD-Grown Al2O3 Gate Insulator

2007 ◽  
Vol 556-557 ◽  
pp. 787-790 ◽  
Author(s):  
Shiro Hino ◽  
Tomohiro Hatayama ◽  
Naruhisa Miura ◽  
Tatsuo Oomori ◽  
Eisuke Tokumitsu
Keyword(s):  
Photoelectron Spectroscopy ◽  
Chemical Vapor ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Organic Chemical ◽  
Mos Capacitors ◽  
Significant Difference ◽  
Metal Organic

We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.

Improved Field Effect Mobility in Si-Face 4H-SiC MOSFETs with a Deposited SiNx Interface Layer

2019 ◽  
Vol 963 ◽  
pp. 469-472 ◽  
Author(s):  
Teruaki Kumazawa ◽  
Mitsuo Okamoto ◽  
Miwako Iijima ◽  
Yohei Iwahashi ◽  
Shinji Fujikake ◽  
...  
Keyword(s):  
Field Effect ◽  
Atomic Layer ◽  
Interface Layer ◽  
Interface State ◽  
State Density ◽  
Field Effect Mobility ◽  
Optimal Thickness ◽  
Interface Quality ◽  
Mos Devices ◽  
Layer Deposition

The SiO2/SiC interface quality has a significant effect on the performance of 4H-SiC MOS devices. The introduction of nitrogen to the SiO2/SiC interface is a well-known method for reducing the interface state density (Dit). In this study, we introduced nitrogen to the SiO2/SiC interface by forming SiNx films using atomic layer deposition (ALD) and thus improved the interface quality. O2 annealing with a SiNx interface layer of optimal thickness enhanced the field effect mobility.

Properties of SiO2/4H-SiC Interfaces with an Oxide Deposited by a High-Temperature Process

2017 ◽  
Vol 897 ◽  
pp. 331-334 ◽  
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Ferdinando Iucolano ◽  
Andrea Severino ◽  
Simona Lorenti ◽  
...  
Keyword(s):  
High Temperature ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Semiconductor Interface ◽  
Mos Capacitors ◽  
High Temperature Process ◽  
Lower Temperature

This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.

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