High K / Metal Gate of Short-Channel SOI NMOSFET Research

2011 ◽  
Vol 383-390 ◽  
pp. 6902-6907
Author(s):  
Gang Lu ◽  
Bo Zhao
Keyword(s):  
Electrical Properties ◽  
Theoretical Analysis ◽  
Leakage Current ◽  
Device Performance ◽  
Gate Leakage Current ◽  
Metal Gate ◽  
Short Channel ◽  
Gate Structure ◽  
High K ◽  
Simulation Results

Short-channel under TaCN/La2O3gate structure SOI NMOSFET has been studied in this paper, contrast with the traditional gate structure gate leakage current and others electrical properties, using TaCN/La2O3gate structure，significantly improved short-channel device performance etc. Additionally, the gate structure in the L=40nm, 30nm and 20nm of C-V characteristic and output characteristic are also studied; all the simulation results coincide with the theoretical analysis.

scholarly journals The Improvement of Reliability of High-k/Metal Gate pMOSFET Device with Various PMA Conditions

2012 ◽  
Vol 2012 ◽  
pp. 1-4
Author(s):  
Yi-Lin Yang ◽  
Wenqi Zhang ◽  
Chi-Yun Cheng ◽  
Wen-kuan Yeh
Keyword(s):  
Leakage Current ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Metal Gate ◽  
Threshold Voltages ◽  
High K ◽  
Nitrogen Annealing

The oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. Both the oxygen and nitrogen annealing will reduce the gate leakage current without increasing oxide thickness. The threshold voltages of the devices changed with various PMA conditions. The reliability of the devices, especially for the oxygen annealed devices, was improved after PMA treatments.

Removing W Polymer Residue from BEOL Structures Using DSP+ (Dilute Sulfuric-Peroxide-HF) Mixture – A Case Study

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park
Keyword(s):  
High Speed ◽  
Semiconductor Device ◽  
Environmental Issues ◽  
Low Power Consumption ◽  
Device Performance ◽  
Metal Gate ◽  
Feature Size ◽  
High K ◽  
Removal Of Metal

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Wet Process Developments for Electrical Properties Improvement Of 3D MIM Capacitors

2007 ◽  
Vol 134 ◽  
pp. 379-382
Author(s):  
Claire Therese Richard ◽  
D. Benoit ◽  
S. Cremer ◽  
L. Dubost ◽  
B. Iteprat ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Copper Oxide ◽  
Leakage Current ◽  
Breakdown Voltage ◽  
3D Structure ◽  
Wet Process ◽  
High K ◽  
3D Architecture ◽  
High K Dielectric ◽  
Mim Capacitors

3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.

scholarly journals Energy-dispersive x-ray spectrum simulation and emprical observation of 22nm node high-k metal gate structure

2015 ◽  
Vol 21 (S3) ◽  
pp. 1785-1786
Author(s):  
Imen Rezadad ◽  
Brenda Prenitzer ◽  
Stephen Schwarz ◽  
Brian Kempshall ◽  
Robert Peale
Keyword(s):  
Energy Dispersive ◽  
Metal Gate ◽  
X Ray ◽  
Gate Structure ◽  
High K ◽  
Spectrum Simulation

Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme

2009 ◽  
Vol 145-146 ◽  
pp. 207-210 ◽  
Author(s):  
Farid Sebaai ◽  
Jose Ignacio Del Agua Borniquel ◽  
Rita Vos ◽  
Philippe Absil ◽  
Thomas Chiarella ◽  
...  
Keyword(s):  
Integration Scheme ◽  
Device Performance ◽  
New Materials ◽  
Metal Gate ◽  
Speed Increase ◽  
Poly Silicon ◽  
High K ◽  
Consumption Reduction ◽  
High K Materials ◽  
Scaling Features

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

First-principles studies of the intrinsic effect of nitrogen atoms on reduction in gate leakage current through Hf-based high-k dielectrics

2005 ◽  
Vol 86 (14) ◽  
pp. 143507 ◽  
Author(s):  
N. Umezawa ◽  
K. Shiraishi ◽  
T. Ohno ◽  
H. Watanabe ◽  
T. Chikyow ◽  
...  
Keyword(s):  
Leakage Current ◽  
First Principles ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
High K ◽  
Intrinsic Effect

scholarly journals Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Short Channel ◽  
High K ◽  
Analog Performance ◽  
Tin Metal ◽  
High K Dielectric ◽  
The Impact

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

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