Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme

2009 ◽  
Vol 145-146 ◽  
pp. 207-210 ◽  
Author(s):  
Farid Sebaai ◽  
Jose Ignacio Del Agua Borniquel ◽  
Rita Vos ◽  
Philippe Absil ◽  
Thomas Chiarella ◽  
...  
Keyword(s):  
Integration Scheme ◽  
Device Performance ◽  
New Materials ◽  
Metal Gate ◽  
Speed Increase ◽  
Poly Silicon ◽  
High K ◽  
Consumption Reduction ◽  
High K Materials ◽  
Scaling Features

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

Material Loss Impact on Device Performance for 32nm CMOS and Beyond

2009 ◽  
Vol 145-146 ◽  
pp. 245-248 ◽  
Author(s):  
Brian K. Kirkpatrick ◽  
James J. Chambers ◽  
Steven L. Prins ◽  
Deborah J. Riley ◽  
Wei Ze Xiong ◽  
...  
Keyword(s):  
Process Control ◽  
Device Performance ◽  
Semiconductor Technology ◽  
New Materials ◽  
Metal Gate ◽  
Material Loss ◽  
Front End ◽  
High K ◽  
Physical Features

As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

Removing W Polymer Residue from BEOL Structures Using DSP+ (Dilute Sulfuric-Peroxide-HF) Mixture – A Case Study

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park
Keyword(s):  
High Speed ◽  
Semiconductor Device ◽  
Environmental Issues ◽  
Low Power Consumption ◽  
Device Performance ◽  
Metal Gate ◽  
Feature Size ◽  
High K ◽  
Removal Of Metal

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.

Surface Preparations Impact on 248nm Deep UV Photo Resists Adhesion during a Wet Etch

2012 ◽  
Vol 195 ◽  
pp. 58-61 ◽  
Author(s):  
Mathieu Foucaud ◽  
Philippe Garnier ◽  
Vincent Joseph ◽  
Erwine Pargon ◽  
Névine Rochat ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Integration Scheme ◽  
Metal Gate ◽  
Covalent Bonds ◽  
Gate Oxides ◽  
Process Step ◽  
High K ◽  
Lift Off ◽  
Wet Etch

Integrated circuits manufacturing still requires several wet etching operations in presence of photo resist. They are usually used to define the gate oxides or metal in a high k metal gate, gate first integration scheme. During this process step, the resist is used for masking and prevents the underneath material from being etched away. Wet treatments are preferred to plasma etching to perform this operation. Indeed, a smooth channels surface is mandatory to obtain a high carriers mobility. It is then critical to avoid any resist lift-off during the wet treatment in order to guarantee the underlying layers integrity. The observation of the lift-off phenomenon (figure 1) points out two possible root causes: 1) a lateral degradation of the covalent bonds at the interface between the polymer and the underlying material, and 2) a vertical resist degradation, due to the penetration of the etching chemicals into the resist down to the underlying material. Previous observations tend to link the lift-off severity to the bake temperature and the oxidation state of the surface on which the resist is coated.

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

Applicable Solvent Photoresist Strip Process for High-K/Metal Gate

2012 ◽  
Vol 187 ◽  
pp. 105-108
Author(s):  
Masayuki Wada ◽  
H. Takahashi ◽  
J. Snow ◽  
Rita Vos ◽  
P.W. Mertens ◽  
...  
Keyword(s):  
High Volume ◽  
Device Fabrication ◽  
New Materials ◽  
Metal Gate ◽  
Technology Innovations ◽  
Integration Schemes ◽  
High K ◽  
Wet Processing ◽  
Near Future ◽  
28 Nm

In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.

Materials and Process Integration Issues in Metal Gate/High-k Stacks and Their Dependence on Device Performance

2019 ◽  
Vol 11 (4) ◽  
pp. 265-274 ◽  
Author(s):  
Alessandro Callegari ◽  
Katherina Babich ◽  
Sufi Zafar ◽  
Vijay Narayanan ◽  
Takashi Ando ◽  
...  
Keyword(s):  
Process Integration ◽  
Device Performance ◽  
Metal Gate ◽  
High K

Study of work function of CVD WSix thin film on high K dielectric.

2003 ◽  
Vol 786 ◽  
Author(s):  
S. Maîtrejean ◽  
S. Allégret ◽  
F. Fillot ◽  
T. Farjot ◽  
B. Guillaumot ◽  
...  
Keyword(s):  
Thin Films ◽  
Work Function ◽  
Dielectric Film ◽  
Oxide Thickness ◽  
Metal Gate ◽  
Mos Capacitors ◽  
Depletion Effect ◽  
High K ◽  
High K Materials ◽  
Nominal Stoichiometry

ABSTRACTTo meet requirements of CMOS circuits at sub 45nm scale, gate oxide thickness shall decrease. Thus high K materials are needed as dielectric gate. In this setting, due to gate depletion effect, metallic material should be used as an alternative to poly silicon gate. Moreover, specifications on threshold voltage require modulation of gate material work function with respect to nMOS or pMOS transistor. WSix work function is known to be sensitive to material stoichiometry. In this work, WSix thin films with x between 2.2 and 2.5 are evaluated as metal gate on HfO2 and SiO2 dielectric. Film chemical characteristics are correlated with work function measurements.Thin films are deposited using WF6 and dichlorosilane on a 200mm wafer industrial chamber. Thermal treatments are applied to sample in order to recrystallise the film and confirm it stability. MOS Capacitors are processed. Electrical characterizations (capacitance vs voltage) are used to extract work function with respect to film composition.Films are chemically and morphologically stable up to 800°C. A W/Si ratio gradient is observed between surface and dielectric/film interface. Whatever the nominal stoichiometry, Si/W ratio is constant at this interface. This result is correlated with identical work function measurement for different nominal stoichiometry. Moreover no differences are observed between Vfb vs equivalent oxide thickness curves for HfO2 and SiO2 dielectric. High EOT variations have been identified for SiO2 capacitors in contrast with SiO2/HfO2 capacitors. These results characterize WSix as a suitable metal gate for nMOS transistors.

High K / Metal Gate of Short-Channel SOI NMOSFET Research

2011 ◽  
Vol 383-390 ◽  
pp. 6902-6907
Author(s):  
Gang Lu ◽  
Bo Zhao
Keyword(s):  
Electrical Properties ◽  
Theoretical Analysis ◽  
Leakage Current ◽  
Device Performance ◽  
Gate Leakage Current ◽  
Metal Gate ◽  
Short Channel ◽  
Gate Structure ◽  
High K ◽  
Simulation Results

Short-channel under TaCN/La2O3gate structure SOI NMOSFET has been studied in this paper, contrast with the traditional gate structure gate leakage current and others electrical properties, using TaCN/La2O3gate structure，significantly improved short-channel device performance etc. Additionally, the gate structure in the L=40nm, 30nm and 20nm of C-V characteristic and output characteristic are also studied; all the simulation results coincide with the theoretical analysis.

Dummy Oxide Removal in High-K Last Process Integration how to Avoid Silicon Corrosion Issue

2012 ◽  
Vol 195 ◽  
pp. 13-16 ◽  
Author(s):  
Farid Sebaai ◽  
Anabela Veloso ◽  
Hiroaki Takahashi ◽  
Antoine Pacco ◽  
Martine Claes ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Process Integration ◽  
Gate Electrode ◽  
Metal Gate ◽  
Poly Silicon ◽  
High K ◽  
Etch Stop ◽  
Etch Stop Layer ◽  
Oxide Removal ◽  
In The Beginning

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).

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