Silicon Wafer Integrated Fan-out Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000217-000247 ◽  
Author(s):  
Curtis Zwenger ◽  
Ron Huemoeller ◽  
JinHan Kim ◽  
DongJean Kim ◽  
WonChul Do ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Low Cost ◽  
Leading Edge ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Integration ◽  
Design Rules ◽  
3D Structures ◽  
3D Packaging ◽  
Thin Film Patterning

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed. A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT package technology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single & multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer level packaging technique. This can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enables the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

Silicon Wafer Integrated Fan-out Technology

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-23 ◽  
Author(s):  
Curtis Zwenger ◽  
George Scott ◽  
Ron Huemoeller ◽  
WonChul Do ◽  
WonGeol Lee ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Low Cost ◽  
Leading Edge ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Integration ◽  
Design Rules ◽  
3D Structures ◽  
3D Packaging ◽  
Thin Film Patterning

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Through Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed. A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT methodology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single and multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer-level packaging technique. The fine feature capabilities can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enable the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile and networking products. SWIFT is a trademark of Amkor Technology, Inc.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Vertical Integration: A Confederacy of Alignment, Bonding, and Materials Technologies

2006 ◽  
Vol 970 ◽  
Author(s):  
Shari Farrens
Keyword(s):  
Error Analysis ◽  
Vertical Integration ◽  
Lower Cost ◽  
Wafer Level ◽  
3D Integration ◽  
Integrated Manufacturing ◽  
Lower Power ◽  
3D Structures ◽  
Pros And Cons ◽  
Cmos Ic

ABSTRACTVertical or 3D integration is taking hold in both the CMOS IC industry and the MEMS industry. The need for smaller devices, lower power, increased functionality, and lower cost are driving the market toward chip and wafer level stacking. Equipment suppliers have been faced with numerous challenges to meet the demands of these emerging bonding applications. This paper will discuss the confederacy of alignment, bonding and materials unions that can lead to successful outcomes in integrated manufacturing.1. Alignment strategies for 3D integration: IR, BSA, and ISA as they pertain to specific bond methods2. Pros and Cons of 3D Bonding Techniques (Direct bonds, metal, adhesive, and eutectic)3. Error analysis in alignment of 3D structures

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Peisheng Liu ◽  
Jinlan Wang ◽  
Liangyu Tong ◽  
Yujuan Tao
Keyword(s):  
Integrated Circuit ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
3D Packaging ◽  
Circuit Fabrication ◽  
Fast Development ◽  
Small Form Factor

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

Reliability and Performance Improvements of 3D System-in-Packages in Fan-Out Wafer Level Packaging

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001458-001485
Author(s):  
Scott Hayes ◽  
Tony Gong ◽  
Doug Mitchell ◽  
Michael Vincent ◽  
Jason Wright ◽  
...  
Keyword(s):  
Wafer Level ◽  
Low Loss ◽  
3D Integration ◽  
Performance Improvements ◽  
Wafer Level Packaging ◽  
Effective System ◽  
3D Packaging ◽  
And Performance ◽  
Imaging Sensors ◽  
2D And 3D

Recent development efforts for fan-out wafer level packaging (FO-WLP) have focused on system-in-package (SiP) solutions using both 2D and 3D packaging structures. Creating connections between the various elements of the system is one of the critical requirements of the packaging technology. The connections must provide a low loss pathway, exhibit manufacturability and prove reliable. Effective system connections enable complex yet volumetrically and electrically efficient systems to be constructed. The combination of various system elements including, but not limited to, SMDs, CMOS, GaAs, MEMS, power devices, imaging sensors or IPDs gives system designers the capability to generate novel systems and differentiating solutions. Both 2D and 3D SiPs based upon the Redistributed Chi Package (RCP) have been developed for consumer, defense and medical applications. In RCP (i.e. FO-WLP), 2D systems are readily achieved through the use of existing packaging processes, materials and structures. For 3D embodiments, the FO-WLP technology must be expanded. 3D integration in FO-WLP can be achieved with the use of package-on-package (PoP), embedded substrates, package edge connections, die stacking or even TSV approaches. However, a more typical solution to the 3D integration challenge is the through package via (TPV). TPVs can resemble substrate vias but their construction is typically different. Regardless of materials selected or processes used to create the TPV, system connections using a TPV will require a certain level of performance and reliability. Reliability and performance improvements to the 3D RCP technology will be presented.

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-41 ◽  
Author(s):  
Lewis(In Soo) Kang
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Industrial Applications ◽  
System Control ◽  
Wafer Level ◽  
Communication Module ◽  
3D Packaging ◽  
Control Application ◽  
Wafer Level Package

The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.

Wafer Level Integration of MMIC and Microwave IPD with Metal/BCB Multilayer Interconnection Based on Low Resistance Silicon

2011 ◽  
Vol 2011 (1) ◽  
pp. 001067-001073
Author(s):  
Jiajie Tang ◽  
Le Luo
Keyword(s):  
Silicon Wafer ◽  
Integrated Circuit ◽  
Performance Test ◽  
Low Cost ◽  
Cost Effective ◽  
Film Deposition ◽  
Thermal Dissipation ◽  
Shielding Effect ◽  
Wafer Level ◽  
Expansion Matching

A new high-density wafer-level integration of a GaAs based monolithic microwave integrated circuit (MMIC) chip and a microwave integrated passive device (IPD) is presented. This integration technology, an important and IC-compatible option for system-in-package (SiP), utilizes bulk Si fabrication and film deposition based multichip module (MCM-D) process. MMIC is entirely embedded into the silicon wafer while IPDs are integrated on the dielectric layers simultaneously with the metal/BCB multilayer interconnection. Key fabrication processes and crucial technologies are described in detail. Normal silicon wafer is selected as substrate because of its mature processing technology, low cost, good thermal dissipation as well as its thermal expansion matching with GaAs. To obtain excellent microwave performances and good planarization, thick photosensitive BCB of 25um/layer is adopted as dielectric and thus the use of tapered via that is hollow inside or filled by BCB is a cost-effective way to accomplish inter-layer connection instead of Au bump bonding or column used in dry-etch BCB process. Further promotions on microwave performances are achieved by the shielding effect through ground layer coverage on silicon surface and the application of microstrip lines. Several experiment results such as dc inter-layer connection resistance and thermal resistance measurements are complemented to investigate the characteristic of the whole package. The Microwave properties of the integration sample are measured by transmission performance test from 15GHz to 30GHz. The measurement results are analyzed and discussed comparing with the theoretical or simulation results.

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