High Temperature Analog-to-Digital Converter Reliability Testing

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000245-000252 ◽  
Author(s):  
Bruce W. Ohme ◽  
Mark R. Larson
Keyword(s):  
High Temperature ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Reliability Testing ◽  
Test Results ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Life Test ◽  
Analog To Digital ◽  
Post Stress

Initial test results have been previously reported for a high-temperature (225°C) 12-bit analog-to-digital converter (HTADC12) fabricated using a production high-temperature silicon-on-insulator (SOI) CMOS process and assembled in hermetically sealed ceramic packages (ref. 1). Reliability test results for the HTADC12 are presented including parametric and functional test results from 1500 hours of dynamic life test at 250°C as well 1000 temperature cycles from −65°C to 200°C. Results of post-stress wirebond, and die bond testing are also provided.

scholarly journals Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 137 ◽  
Author(s):  
Bo Gao ◽  
Xin Li ◽  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Noise ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
High Bandwidth

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

scholarly journals A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 165
Author(s):  
Shouping Li ◽  
Yang Guo ◽  
Jianjun Chen ◽  
Bin Liang
Keyword(s):  
Successive Approximation ◽  
High Speed ◽  
Low Noise ◽  
Digital Calibration ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

scholarly journals Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

2015 ◽  
Vol 37 (1) ◽  
pp. 33 ◽  
Author(s):  
Al Al ◽  
Mamun Bin Ibne Reaz ◽  
Jubayer Jalil ◽  
Mohd. Alauddin Mohd. Ali
Keyword(s):  
Low Power ◽  
Temperature Sensors ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital

scholarly journals Investigation of a spatial optical pulse collection system in the all-optical analog-to-digital converter

2005 ◽  
Author(s):  
◽  
Wen-Ren Yang
Keyword(s):  
Integrated Circuit ◽  
Structural Changes ◽  
Spatial Filter ◽  
Calculation Model ◽  
Silicon On Insulator ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
All Optical ◽  
Optical Analog

In this research, I conducted a systematic integration of specific calculations for the analysis of the spatial filter that is a critical component of an all-optical analog-to-digital converter. The designed all-optical analog-to-digital converter has special relevance for high-resolution [x] bandwidth applications such as radar image processing. The design of the spatial filter array is based on the silicon-on-insulator process, a design that fulfills requirements of both lower power consumption and smaller integrated circuit chip size. For the developed calculation model, Babinet's principle is used in order to decompose a complicated structure into different simple components. The decomposed structure is analyzed by modifying the existing diffraction calculation methods. The method of calculating the transmission ratio of the propagating electric field compared to the finite-different-time-domain method is a new approach. The systematic integration is also adaptive to changes in the spatial filter's components. Structural changes do not require changes to the entire calculation model.

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

Lifetime and Failure Modes of High Temperature SOI Products

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000112-000115 ◽  
Author(s):  
Derek Maxwell ◽  
Marshall Soares ◽  
Matt Coreless
Keyword(s):  
High Temperature ◽  
Failure Modes ◽  
Extreme Temperature ◽  
Silicon On Insulator ◽  
Accelerated Testing ◽  
Test Results ◽  
Life Test ◽  
Tungsten Metal

Abstract RelChip has performed life test studies on its RAM and has shown that Silicon On Insulator (SOI) processing with Aluminum-Tungsten metal traces can operate for over 4000 hours at 350°C and do not fail due to electromigration. Three parts were randomly selected and functionally tested at the extreme temperature using accelerated testing (HAST). The parts were pulled periodically for in-depth testing and examination. Test results indicate failures are due to device failures, and not electromigration.

High Temperature 256Kbit (32Kbit × 8) HTEEPROM Reliability Testing

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000105-000115
Author(s):  
Joe G. Guimont ◽  
Bruce W. Ohme
Keyword(s):  
High Temperature ◽  
Gas Analysis ◽  
Silicon On Insulator ◽  
Reliability Test ◽  
Cmos Process ◽  
Control Input ◽  
Test Results ◽  
Data Retention ◽  
Parallel Memory ◽  
Non Volatile Memory

Results of reliability and qualification testing are presented for a commercial High Temperature EEPROM (HTEEPROM). This HTEEPROM is specified for operation at 225°C and is the highest temperature rated commercial non-volatile memory available to date. Initial test results (at 250°C) and design details have been previously reported for a prototype 256Kbit (32Kbit × 8) HTEEPROM fabricated using a production high-temperature silicon-on-insulator (SOI) 0.8 micron CMOS process [1]. This paper presents reliability test results for a commercial version developed using knowledge gained from the previously reported HTEEPROM, and fabricated in the same technology. The reliability test results include data retention at 250°C, endurance (write cycling) > 100,000 cycles, parametric and functional test results for 1000 hours of dynamic life test at 250°C, 100 temperature cycles from −65°C to 200°C, ESD, Group D and residual-gas-analysis (RGA) testing. The HTEEPROM is packaged in a 56-pin ceramic pin-grid-array (PGA) package. It is configurable by a control input pin for either serial or parallel memory access. The design incorporates an on-chip timer to support periodic memory refresh to extend data retention indefinitely.

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