Location of the Critical Solder Joint of a PBGA under Temperature Cycling Load for SAC and SnPb Solder. Results of Experiments vs. FE-Simulations on System and Board Level.

2011 ◽  
Vol 2011 (1) ◽  
pp. 000409-000417 ◽  
Author(s):  
Natalja Schafet ◽  
Bruno Schrempp ◽  
Manfred Spraul ◽  
Ulrich Becker ◽  
Herbert Güttler
Keyword(s):  
Solder Joints ◽  
Mechanical Strain ◽  
Temperature Cycling ◽  
System Level ◽  
Transient Temperature ◽  
Snagcu Solder ◽  
System Level Simulation ◽  
Solder Balls ◽  
Board Level ◽  
Sac Solder

PBGAs with SnPb and SnAgCu (SAC) solder joints were stressed with temperature cycles on board- and system-level. A significant influence of the different solder materials on the location of the most damaged PBGA solder balls was observed in the experiment. The reason for this experimental finding was investigated and explained by FE–simulation. The simulations of the PBGAs were done on package-, board- and system-level (PCB within a metal housing). For the system level simulation a 2-step sub-model technique described in [1] was used. Through such an approach the transient PCB deformation and the transient temperature field within the ECU-housing can be incorporated into a creep simulation of the PBGA solder joints. The creep results for both SnPb and SnAgCu solder joints from the board- and system-level simulation were compared. The calculated damage factor due to the ECU-housing influence is different for PBGA with SnPb and SAC solder joints. The simulation results were validated step by step with measurements and experiments: warpage of the non-soldered PBGA, mechanical strain and temperature on the mounted PCB, crack length evaluation of all PBGA solder joints.

scholarly journals Sporadic Early Life Solder Ball Detachment Effects on Subsequent Microstructure Evolution and Fatigue of Solder Joints in Wafer-Level Chip-Scale Packages

2020 ◽  
Vol 17 (1) ◽  
pp. 13-22
Author(s):  
Simon Schambeck ◽  
Matthias Hutter ◽  
Johannes Jaeschke ◽  
Andrea Deutinger ◽  
Martin Schneider-Ramelow
Keyword(s):  
Thermal Loading ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Aging Effects ◽  
Chip Scale Package ◽  
Solder Balls

Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packaging technology. One aspect is to increase the understanding of the damage under environmental loading. Therefore, the solder joints of a wafer-level chip-scale package assembled on a printed circuit board (PCB) have been analyzed after a temperature cycling test. In the case of the investigated package, a limited number of joints did not form a proper mechanical connection with the PCB copper pad. Although not intended in the first place, these circumstances cause a detachment of those joints within the first few thermal cycles. However, this constellation offers a unique opportunity to compare the solder joint microstructure after thermomechanical loading (connected joints) with pure thermal loading (detached joints) located directly next to each other. It is shown that microstructure aging effects can be directly linked to regions in the joint with increased loading. This is particularly the case for detached joints, which could almost retain their initial microstructure up to the effect of the high-temperature part of the thermal profile. By means of finite element simulation, it is further possible to quantify the increased loading on adjacent joints if isolated solder balls detach from the board. In one case presented, the lifetime of the corner joint was calculated to reduce up to 85% only.

Electromigration Performance of WLPs with Standard and Polymer Core Balls

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002361-002392
Author(s):  
L. Nguyen ◽  
H. Nguyen ◽  
A. Prabhu
Keyword(s):  
Failure Modes ◽  
Void Formation ◽  
Solid Polymer ◽  
Current Crowding ◽  
Wafer Level ◽  
San Jose ◽  
Snagcu Solder ◽  
Wafer Level Packaging ◽  
Solder Balls ◽  
Board Level

This talk will compare the electromigration performance of wafer level packages having standard SnAgCu solder with those having solder balls with polymer cores. Information on package construction, process, and board level reliability of packages having balls with polymer cores was presented earlier (2009 International Wafer Level Packaging Conference, San Jose, CA). In the new ball variation, the structure is made of a large solid polymer core, which is plated with a thin layer of copper and covered with a layer of SnAg. The polymer core within the solder ball ensures that the standoff height remains constant during board assembly, and acts as a stress absorption layer between the Si and the PCB during any thermal excursion and drop testing. Such characteristics allow extension of the wafer level package from small pin count (~30 I/O) to higher pin count (100+ I/O) without the need for redistribution layers. For electromigration, bump resistances were monitored continuously at different current densities and temperatures for the two package types. Equivalent performance was obtained. Similar failure modes were observed in both cases, with pancake-like void formation growing outward from the pad corners due to current crowding. Equivalent performance was obtained, with both packages exhibiting MTTF of 1200 hrs at 150C, and 550 hrs at 165C. Application to a modified Black's equation to predict MTTF and account for current crowding, heating, and stress will also be discussed.

scholarly journals System Level Simulation of Microgrid Power Electronic Systems

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 644
Author(s):  
Michal Frivaldsky ◽  
Jan Morgos ◽  
Michal Prazenica ◽  
Kristian Takacs
Keyword(s):  
Smart Grid ◽  
Simulation Model ◽  
Real Time ◽  
Power Converter ◽  
System Level ◽  
Time Behavior ◽  
Operational Parameters ◽  
System Level Simulation ◽  
Time Operation ◽  
The Impact

In this paper, we describe a procedure for designing an accurate simulation model using a price-wised linear approach referred to as the power semiconductor converters of a DC microgrid concept. Initially, the selection of topologies of individual power stage blocs are identified. Due to the requirements for verifying the accuracy of the simulation model, physical samples of power converters are realized with a power ratio of 1:10. The focus was on optimization of operational parameters such as real-time behavior (variable waveforms within a time domain), efficiency, and the voltage/current ripples. The approach was compared to real-time operation and efficiency performance was evaluated showing the accuracy and suitability of the presented approach. The results show the potential for developing complex smart grid simulation models, with a high level of accuracy, and thus the possibility to investigate various operational scenarios and the impact of power converter characteristics on the performance of a smart gird. Two possible operational scenarios of the proposed smart grid concept are evaluated and demonstrate that an accurate hardware-in-the-loop (HIL) system can be designed.

Board-Level Reliability of Pb-Free Surface Mounted Assemblies during Thermal Shock Testing

2006 ◽  
Vol 15-17 ◽  
pp. 633-638 ◽  
Author(s):  
Jong Woong Kim ◽  
Hyun Suk Chun ◽  
Sang Su Ha ◽  
Jong Hyuck Chae ◽  
Jin Ho Joo ◽  
...  
Keyword(s):  
Thermal Shock ◽  
Solder Joints ◽  
Lead Frame ◽  
Shear Forces ◽  
Microstructural Investigation ◽  
Shock Testing ◽  
Ceramic Capacitor ◽  
Board Level ◽  
Board Level Reliability ◽  
Thermal Shocks

Board-level reliability of conventional Sn-37Pb and Pb-free Sn-3.0Ag-0.5Cu solder joints was evaluated using thermal shock testing. In the microstructural investigation of the solder joints, the formation of Cu6Sn5 intermetallic compound (IMC) layer was observed between both solders and Cu lead frame, but any crack or newly introduced defect cannot be found even after 2000 cycles of thermal shocks. Shear test of the multi layer ceramic capacitor (MLCC) joints were also conducted to investigate the effect of microstructural variations on the bonding strength of the solder joints. Shear forces of the both solder joints decreased with increasing thermal shock cycles. The reason to the decrease in shear force was discussed with fracture surfaces of the shear tested solder joints.

A rig for controlled cyclic strain and temperature testing

1982 ◽  
Vol 17 (1) ◽  
pp. 45-52 ◽  
Author(s):  
D J Beauchamp ◽  
E G Ellison
Keyword(s):  
Mechanical Strain ◽  
Thermal Strain ◽  
Cyclic Strain ◽  
Heating System ◽  
Temperature Cycle ◽  
Transient Temperature ◽  
Microprocessor System ◽  
Hydraulic Test ◽  
Heating And Cooling ◽  
Phase Temperature

A servo-hydraulic test rig capable of applying combined temperature and strain or load cycles has been developed and commissioned. The nature of the test has dictated the specimen form as a hollow, hour-glass type. The critical problem of a suitable extensometer for temperature and strain cycling has been solved. The device designed and produced shows negligible transient temperature effects, has a high resolution of better than 0.1 μm, and is mechanically very stable. The heating and cooling is controlled by an induction heating system with grip cooling; additional cooling is available using compressed air passing through the hollow specimen. The system is capable of following a temperature ramp to within 1°C linearity. The thermal strain associated with a temperature cycle is compensated for using a microprocessor system specially developed for the purpose, which also enables a mechanical strain-stress loop to be plotted during a test. Both ‘in-phase’ and ‘out-of-phase’ temperature/strain cycles have been carried out and development continues to include dwell periods.

scholarly journals Gem5-X

2021 ◽  
Vol 18 (4) ◽  
pp. 1-27
Author(s):  
Yasir Mahmood Qureshi ◽  
William Andrew Simon ◽  
Marina Zapater ◽  
Katzalin Olcoz ◽  
David Atienza
Keyword(s):  
Visual Recognition ◽  
Energy Savings ◽  
Video Encoding ◽  
System Level ◽  
Heterogeneous Architecture ◽  
Video Analytics ◽  
Smart Systems ◽  
System Level Simulation ◽  
Many Core ◽  
New Applications

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this article, we present gem5-X, a system-level simulation framework, based on gem-5, for architectural exploration of heterogeneous many-core systems. To demonstrate the capabilities of gem5-X, real-time video analytics is used as a case-study. It is composed of two kernels, namely, video encoding and image classification using convolutional neural networks (CNNs). First, we explore through gem5-X the benefits of latest 3D high bandwidth memory (HBM2) in different architectural configurations. Then, using a two-step exploration methodology, we develop a new optimized clustered-heterogeneous architecture with HBM2 in gem5-X for video analytics application. In this proposed clustered-heterogeneous architecture, ARMv8 in-order cluster with in-cache computing engine executes the video encoding kernel, giving 20% performance and 54% energy benefits compared to baseline ARM in-order and Out-of-Order systems, respectively. Furthermore, thanks to gem5-X, we conclude that ARM Out-of-Order clusters with HBM2 are the best choice to run visual recognition using CNNs, as they outperform DDR4-based system by up to 30% both in terms of performance and energy savings.

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