Electromigration Performance of WLPs with Standard and Polymer Core Balls

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002361-002392
Author(s):  
L. Nguyen ◽  
H. Nguyen ◽  
A. Prabhu
Keyword(s):  
Failure Modes ◽  
Void Formation ◽  
Solid Polymer ◽  
Current Crowding ◽  
Wafer Level ◽  
San Jose ◽  
Snagcu Solder ◽  
Wafer Level Packaging ◽  
Solder Balls ◽  
Board Level

This talk will compare the electromigration performance of wafer level packages having standard SnAgCu solder with those having solder balls with polymer cores. Information on package construction, process, and board level reliability of packages having balls with polymer cores was presented earlier (2009 International Wafer Level Packaging Conference, San Jose, CA). In the new ball variation, the structure is made of a large solid polymer core, which is plated with a thin layer of copper and covered with a layer of SnAg. The polymer core within the solder ball ensures that the standoff height remains constant during board assembly, and acts as a stress absorption layer between the Si and the PCB during any thermal excursion and drop testing. Such characteristics allow extension of the wafer level package from small pin count (~30 I/O) to higher pin count (100+ I/O) without the need for redistribution layers. For electromigration, bump resistances were monitored continuously at different current densities and temperatures for the two package types. Equivalent performance was obtained. Similar failure modes were observed in both cases, with pancake-like void formation growing outward from the pad corners due to current crowding. Equivalent performance was obtained, with both packages exhibiting MTTF of 1200 hrs at 150C, and 550 hrs at 165C. Application to a modified Black's equation to predict MTTF and account for current crowding, heating, and stress will also be discussed.

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

2017 ◽  
Vol 14 (4) ◽  
pp. 123-131 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Location of the Critical Solder Joint of a PBGA under Temperature Cycling Load for SAC and SnPb Solder. Results of Experiments vs. FE-Simulations on System and Board Level.

2011 ◽  
Vol 2011 (1) ◽  
pp. 000409-000417 ◽  
Author(s):  
Natalja Schafet ◽  
Bruno Schrempp ◽  
Manfred Spraul ◽  
Ulrich Becker ◽  
Herbert Güttler
Keyword(s):  
Solder Joints ◽  
Mechanical Strain ◽  
Temperature Cycling ◽  
System Level ◽  
Transient Temperature ◽  
Snagcu Solder ◽  
System Level Simulation ◽  
Solder Balls ◽  
Board Level ◽  
Sac Solder

PBGAs with SnPb and SnAgCu (SAC) solder joints were stressed with temperature cycles on board- and system-level. A significant influence of the different solder materials on the location of the most damaged PBGA solder balls was observed in the experiment. The reason for this experimental finding was investigated and explained by FE–simulation. The simulations of the PBGAs were done on package-, board- and system-level (PCB within a metal housing). For the system level simulation a 2-step sub-model technique described in [1] was used. Through such an approach the transient PCB deformation and the transient temperature field within the ECU-housing can be incorporated into a creep simulation of the PBGA solder joints. The creep results for both SnPb and SnAgCu solder joints from the board- and system-level simulation were compared. The calculated damage factor due to the ECU-housing influence is different for PBGA with SnPb and SAC solder joints. The simulation results were validated step by step with measurements and experiments: warpage of the non-soldered PBGA, mechanical strain and temperature on the mounted PCB, crack length evaluation of all PBGA solder joints.

Ceramic Via Wafer-Level Packaging for MEMS

2005 ◽  
Author(s):  
John M. Heck ◽  
Leonel R. Arana ◽  
Bill Read ◽  
Thomas S. Dory
Keyword(s):  
Mems Devices ◽  
Wafer Level ◽  
Micro Electro Mechanical Systems ◽  
Mems Switches ◽  
Mems Packaging ◽  
Wafer Level Packaging ◽  
Novel Approach ◽  
Electrical Interconnection ◽  
Tin Silver Copper ◽  
Board Level

We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic gold-tin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)

2017 ◽  
Vol 2017 (1) ◽  
pp. 000576-000583 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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