Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach

2012 ◽  
Vol 2012 (1) ◽  
pp. 000233-000238 ◽  
Author(s):  
Y. Lamy ◽  
S. Joblot ◽  
C. Ferrandon ◽  
J.F. Carpentier ◽  
G. Simon
Keyword(s):  
High Temperature ◽  
Low Cost ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
High Temperature Process ◽  
Bridge Approach ◽  
Different Diameters ◽  
Dry Film

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The top via is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with high temperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs (short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer is backgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE process create the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cu plating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle (AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. The mechanical simulations show that this ″TSV bridge″ has reduced residual stresses inside the TSV. Our electrical measurements exhibit an average single TSV resistance below 10mOhms with excellent yield (∼95% on Kelvin and 82 TSV chains), and low contact resistances (4.7×10−9 Ω.cm2) extrapolated on 4 different contact diameters. This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

BCB-Based Dry Film low k Permanent Polymer with sub 4-μm Vias for Advanced WLP and FO-WLP Applications

2015 ◽  
Vol 2015 (1) ◽  
pp. 000079-000085 ◽  
Author(s):  
Michael Toepper ◽  
Tanja Braun ◽  
Robert Gernhardt ◽  
Martin Wilke ◽  
Piotr Mackowiak ◽  
...  
Keyword(s):  
Laser Scanning ◽  
New Technology ◽  
Side Wall ◽  
Wafer Level ◽  
Major Barrier ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Low K ◽  
Metallization Process ◽  
Dry Film

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

2009 ◽  
Author(s):  
Deniz S. Tezcan ◽  
Fabrice Duval ◽  
Harold Philipsen ◽  
Ole Luhn ◽  
Philippe Soussan ◽  
...  
Keyword(s):  
Wafer Level ◽  
Through Silicon Via ◽  
Deep Trench ◽  
Wafer Level Packaging ◽  
Trench Isolation

scholarly journals Design and Fabrication of Wafer-Level Microlens Array with Moth-Eye Antireflective Nanostructures

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 747 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Bo Yang ◽  
Wei Zhang ◽  
Xiaoxiao Wei ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Production Efficiency ◽  
Low Cost ◽  
Microlens Array ◽  
Wafer Level ◽  
Lens Array ◽  
Wafer Level Packaging ◽  
High Production ◽  
Aspherical Lenses ◽  
Profile Accuracy

Wafer-level packaging (WLP) based camera module production has attracted widespread industrial interest because it offers high production efficiency and compact modules. However, suppressing the surface Fresnel reflection losses is challenging for wafer-level microlens arrays. Traditional dielectric antireflection (AR) coatings can cause wafer warpage and coating fractures during wafer lens coating and reflow. In this paper, we present the fabrication of a multiscale functional structure-based wafer-level lens array incorporating moth-eye nanostructures for AR effects, hundred-micrometer-level aspherical lenses for camera imaging, and a wafer-level substrate for wafer assembly. The proposed fabrication process includes manufacturing a wafer lens array metal mold using ultraprecise machining, chemically generating a nanopore array layer, and replicating the multiscale wafer lens array using ultraviolet nanoimprint lithography. A 50-mm-diameter wafer lens array is fabricated containing 437 accurate aspherical microlenses with diameters of 1.0 mm; each lens surface possesses nanostructures with an average period of ~120 nm. The microlens quality is sufficient for imaging in terms of profile accuracy and roughness. Compared to lenses without AR nanostructures, the transmittance of the fabricated multiscale lens is increased by ~3% under wavelengths of 400–750 nm. This research provides a foundation for the high-throughput and low-cost industrial application of wafer-level arrays with AR nanostructures.

Low-cost wafer level packaging process

2000 ◽  
Author(s):  
Rahul Kapoor ◽  
Swee Y. Khim ◽  
Goh H. Hwa
Keyword(s):  
Low Cost ◽  
Wafer Level ◽  
Packaging Process ◽  
Wafer Level Packaging

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

2012 ◽  
Vol 1427 ◽  
Author(s):  
Hamid Kiumarsi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
Kenichi Okada ◽  
Yusuke Uemichi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Performance ◽  
Low Cost ◽  
Phase Error ◽  
Superior Performance ◽  
60 Ghz ◽  
Wafer Level ◽  
Chip Area ◽  
Wafer Level Packaging ◽  
Coupled Lines

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

Sign in / Sign up

Export Citation Format

Share Document