3D SiP Assembly and Reliability for Glass Substrate with Through Vias

2016 ◽  
Vol 2016 (1) ◽  
pp. 000282-000287
Author(s):  
Ra-Min Tain ◽  
Dyi-Chung Hu ◽  
Kai-Ming Yang ◽  
Yu-Hua Chen ◽  
Jui-Tang Chen ◽  
...  
Keyword(s):  
Glass Substrate ◽  
High Performance ◽  
Printed Circuit Board ◽  
Dielectric Material ◽  
Mechanical Test ◽  
Circuit Board ◽  
Material Structure ◽  
Back Side ◽  
Glass Technology ◽  
Resistance Change

Abstract Applications of Glass substrate for high performance system-in-package (SiP) products have gradually become a promising technology in recent years. Research and development activities are reported in many journal papers and conferences [1,2]. Consortiums and Alliances are also formed to gather worldwide efforts for developing glass technology. In the past, we have published our development efforts on the process of producing glass substrate with through via and build-up redistribution circuit layers (RDLs) [3]. N. Koizumi [4] first reported glass reliability issues in 2013; and the phenomena he called SE-WA-RE has caused a great concern of using glass as a substrate. Model simulations have indicated that the glass crack is related to the stress buildup by the materials and structure. In this study, we selected a dielectric material/structure set that is designed to be less stressful to the glass substrate. A better reliability result can be expected. In this paper, we will discuss an assembly structure of SiP module using the glass substrate with through-glass via (TGV) where the diameter of TGV is 100μm with thickness at 200μm. The copper plating technique to form the through via conductor is called direct-metal-on-glass (DMoG) which deposits titanium and copper directly on glass both in the wall of through vias and on glass surfaces of both sides. The first RDL is formed on both surfaces of glass substrate by semi-additive plating (SAP); then followed by build-up RDLs on top of the DMoG RDLs on both sides of the substrate also by SAP with interconnect vias to form connections between DMoG RDLs and build-up RDLs. Finally, solder mask is applied on both sides of the glass substrate leaving pad openings (SRO) for surface finish, die mounting and printed-circuit board connection purposes. At die mounting side, the SRO is 60μm in diameter with minimum pitch at 150μm. The TGV conductors connect the DMoG RDLs on both sides of the substrate. A mechanical test die with 18μm bump diameter is mounted on the build-up RDL at the substrate top side with daisy-chain design both in the test die and TGV substrate RDLs. Thus, the daisy-chain connection can go from the build-up RDL of the substrate back side to the test die on the top side of the substrate. 200 thermal-cycling test (TCT) has been performed and the daisy-chain resistances are measured before and after the 200 TCTs. It is found that 96% of daisy-chains have less than 10% of resistance change after 200 TCTs.

scholarly journals A Self-Powered Nanogenerator for the Electrical Protection of Integrated Circuits from Trace Amounts of Liquid

2019 ◽  
Vol 12 (1) ◽  
Author(s):  
Zhuang Hui ◽  
Ming Xiao ◽  
Daozhi Shen ◽  
Jiayun Feng ◽  
Peng Peng ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Printed Circuit Board ◽  
Short Circuit ◽  
High Sensitivity ◽  
Short Circuit Current ◽  
Fast Response ◽  
Open Circuit ◽  
Circuit Board ◽  
Self Powered

Abstract With the increase in the use of electronic devices in many different environments, a need has arisen for an easily implemented method for the rapid, sensitive detection of liquids in the vicinity of electronic components. In this work, a high-performance power generator that combines carbon nanoparticles and TiO2 nanowires has been fabricated by sequential electrophoretic deposition (EPD). The open-circuit voltage and short-circuit current of a single generator are found to exceed 0.7 V and 100 μA when 6 μL of water was applied. The generator is also found to have a stable and reproducible response to other liquids. An output voltage of 0.3 V was obtained after 244, 876, 931, and 184 μs, on exposure of the generator to 6 μL of water, ethanol, acetone, and methanol, respectively. The fast response time and high sensitivity to liquids show that the device has great potential for the detection of small quantities of liquid. In addition, the simple easily implemented sequential EPD method ensures the high mechanical strength of the device. This compact, reliable device provides a new method for the sensitive, rapid detection of extraneous liquids before they can impact the performance of electronic circuits, particularly those on printed circuit board.

scholarly journals Design Analysis of a Mobile-Based Gait Analyzer

2019 ◽  
Vol 3 (3) ◽  
Author(s):  
Adedotun Oluwakanyinsola Owojori ◽  
Ibukunoluwa A. Adebanjo ◽  
Samson A. Oyetunji
Keyword(s):  
Hardware Implementation ◽  
Printed Circuit Board ◽  
Dielectric Material ◽  
Circuit Board ◽  
Printed Circuit ◽  
Uniform Distance ◽  
Pressure Mapping ◽  
Short Period ◽  
Mapping Technology ◽  
Processing Circuit

Considering a system capable of identifying abnormalities in people's walking conditions in real-time, simply by studying his/her walking profile over a short period of time is a phenomenal breakthrough in the field of biotechnology. Such abnormalities could be as a result of injury, old age, or disease termed gait which could be analyzed using the pressure mapping technology. Pressure points in the feet of an injured person as he/she walks is analyzed by sets of sensors (capacitive sensors) carefully design with a rectangular 5.1cm by 2cm parallel aluminium plate and placed on developed footwear with a uniform distance of 1cm across the dielectric material. The output of the pre-processing stage gives varying values which are calibrated and sent to the microcontroller. All placed on a portable sized Printed Circuit Board (PCB) making it moveable from one place to another (that is, mobile), is the pre-processing circuit that converts measured or evaluated result to the transmittable signal through a Mobile Communication System which can be received on a Personal Computer (PC) in form of a periodic chat and/ or report. The result of the analysis is shown both in simulation and hardware implementation of the system

scholarly journals A Dual Band Slotted Patch Antenna on Dielectric Material Substrate

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
M. Habib Ullah ◽  
M. T. Islam ◽  
M. R. Ahsan ◽  
J. S. Mandeep ◽  
N. Misran
Keyword(s):  
Patch Antenna ◽  
Printed Circuit Board ◽  
Dielectric Material ◽  
Circuit Board ◽  
Dual Band ◽  
Polymer Resin ◽  
Full Wave ◽  
Low Profile ◽  
Gain Variation ◽  
Satellite Applications

A low profile, compact dual band slotted patch antenna has been designed using finite element method-based high frequency full-wave electromagnetic simulator. The proposed antenna fabricated using LPKF printed circuit board (PCB) fabrication machine on fiberglass reinforced epoxy polymer resin material substrate and the performance of the prototype has been measured in a standard far-field anechoic measurement chamber. The measured impedance bandwidths of (reflection coefficient<-10 dB) 12.26% (14.3–16.2 GHZ), 8.24% (17.4–18.9 GHz), and 3.08% (19.2–19.8) have been achieved through the proposed antenna prototype. 5.9 dBi, 3.37 dBi, and 3.32 dBi peak gains have been measured and simulated radiation efficiencies of 80.3%, 81.9%, and 82.5% have been achieved at three resonant frequencies of 15.15 GHz, 18.2 GHz, and 19.5 GHz, respectively. Minimum gain variation, symmetric, and almost steady measured radiation pattern shows that the proposed antenna is suitable for Ku and K band satellite applications.

scholarly journals HIGH-PERFORMANCE FLEXIBLE FORCE AND TEMPERATURE SENSING ARRAY WITH A ROBUST STRUCTURE

2013 ◽  
Vol 24 ◽  
pp. 1360014
Author(s):  
MIN-SEOK KIM ◽  
HAN-WOOK SONG ◽  
YON-KYU PARK
Keyword(s):  
High Performance ◽  
Sensor Array ◽  
Printed Circuit Board ◽  
High Spatial Resolution ◽  
Tactile Sensor ◽  
Circuit Board ◽  
Micro Fabrication ◽  
Printed Circuit ◽  
Flexible Printed Circuit ◽  
Physical Quantities

We have developed a flexible tactile sensor array capable of sensing physical quantities, e.g. force and temperature with high-performances and high spatial resolution. The fabricated tactile sensor consists of 8 × 8 force measuring array with 1 mm spacing and a thin metal (copper) temperature sensor. The flexible force sensing array consists of sub-millimetre-size bar-shaped semi-conductor strain gage array attached to a thin and flexible printed circuit board covered by stretchable elastomeric material on both sides. This design incorporates benefits of both materials; the semi-conductor's high performance and the polymer's mechanical flexibility and robustness, while overcoming their drawbacks of those two materials. Special fabrication processes, so called “dry-transfer technique” have been used to fabricate the tactile sensor along with standard micro-fabrication processes.

Macro and Micro Thermal Model of an Elevated Temperature Dielectric Breakdown in Printed Circuit Boards

1996 ◽  
Author(s):  
R. Stutzman ◽  
S. Sathe ◽  
B. Sammakia
Keyword(s):  
Thermal Model ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Dielectric Breakdown ◽  
Dielectric Material ◽  
High Current Density ◽  
Thermal Modeling ◽  
Circuit Board ◽  
Printed Circuit ◽  
Defect Site

Abstract A computational macro and micro thermal model of a printed circuit board dielectric breakdown due to local and global heating of the laminate material is presented in this paper. On a macro level, under certain conditions, the circuit board temperature can approach the glass transition temperature (Tg) due to electronic surface mounted components dissipating heat to the board surface. Under these conditions interfacial micro cracks or dielectric inhomogeneities can be aggravated to an extent where localized voltage breakdown can occur across copper planes within the board. The micro thermal modeling results demonstrate that even under relatively high defect resistance levels the localized temperature at the defect site can greatly exceed the Tg of the dielectric material resulting in carbonization and eventually catastrophic failure. A temperature profile at the defect site clearly shows the spike in the local temperature due to the low thermal conductivity properties of the dielectric material and the localized high current density. The thermal modeling was performed using Flotherm (trademark of Flomerics Limited) code.

Enabling High-Performance Heterogeneous Integration via Interface Standards, IP Reuse, and Modular Design

2018 ◽  
Vol 2018 (1) ◽  
pp. 000246-000251
Author(s):  
Andreas Olofsson ◽  
Daniel S. Green ◽  
Jeffrey Demmin
Keyword(s):  
High Performance ◽  
Printed Circuit Board ◽  
Modular Design ◽  
Semiconductor Industry ◽  
Leading Edge ◽  
Cost Effective ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Prohibitive Cost ◽  
Ip Reuse

Abstract DARPA is leading a new thrust to leverage mainstream semiconductor design approaches to enable the rapid and cost-effective integration of heterogeneous device technologies. This represents a leap ahead beyond the monolithic silicon approach that has served the semiconductor industry well, but which now creates prohibitive cost and design issues at leading-edge nodes, as well as performance constraints without the benefits of broad device technology options. DARPA's Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will develop interface standards, IP reuse methodologies, and modular design approaches with the goal of making heterogeneous integration as straightforward as printed circuit board design and assembly, without compromising device performance. An overview of the program's vision, goals, and progress to date is presented here.

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