scholarly journals DESIGN METHODOLOGY OF BIDIRECTIONAL BARREL SHIFTER BASED ON REVERSIBLE LOGIC

2013 ◽  
pp. 50-55
Author(s):  
V. SRUJANA ◽  
G. BABU
Keyword(s):  
High Speed ◽  
Design Methodology ◽  
Quantum Computer ◽  
Critical Path ◽  
Computer Arithmetic ◽  
Reversible Logic ◽  
Logic Design ◽  
Quantum Cost ◽  
Single Cycle ◽  
Fredkin Gate

Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated.

scholarly journals DESIGN OF AN EFFICIENT REVERSIBLE LOGIC BASED BIDIRECTIONAL BARREL SHIFTER

2013 ◽  
pp. 115-120
Author(s):  
O. ANJANEYULU ◽  
T. PRADEEP ◽  
C.V. KRISHNA REDDY
Keyword(s):  
High Speed ◽  
Optical Computing ◽  
Digital Signal ◽  
General Purpose ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Fredkin Gate ◽  
Barrel Shifter ◽  
Proportional Increase ◽  
Signal Processors

Embedded digital signal processors and general purpose processors will use barrel shifters to manipulate data. This paper will present the design of the barrel shifter that performs logical shift right, arithmetic shift right, rotate right, logical shift left, arithmetic shift left, and rotate left operations. The main objective of the upcoming designs is to increase the performance without proportional increase in power consumption. In this regard reversible logic has become most popular technology in the field of low power computing, optical computing, quantum computing and other computing technologies. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated.

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

scholarly journals High functionality reversible arithmetic logic unit

2020 ◽  
Vol 10 (3) ◽  
pp. 2329
Author(s):  
Shaveta Thakral ◽  
Dipali Bansal
Keyword(s):  
Power Dissipation ◽  
Logic Gates ◽  
Reversible Logic ◽  
Logic Design ◽  
Quantum Cost ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Reversible Logic Gates ◽  
Reversible Alu ◽  
Logic Unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

scholarly journals Design Methodologies for Reversible Logic Based Barrel Shifters

2015 ◽  
Vol 25 (02) ◽  
pp. 1650003
Author(s):  
Saurabh Kotiyal ◽  
Himanshu Thapliyal
Keyword(s):  
Optical Computing ◽  
Reversible Logic ◽  
The Other ◽  
Quantum Cost ◽  
Design Methodologies ◽  
Fredkin Gate ◽  
Barrel Shifter ◽  
Minimum Number ◽  
Feynman Gate ◽  
Ancilla Inputs

Barrel shifter is an integral component of processor datapaths in computing systems since it can shift and rotate multiple bits in a single cycle. Furthermore, reversible logic has applications in emerging computing paradigms such as quantum computing, quantum dot cellular automata, optical computing, etc. In this work, we propose efficient methodologies for designing reversible barrel shifters. The proposed methodologies are designed using Fredkin gate and Feynman gate (FG). The Fredkin gate is used because it can implement a 2:1 MUX with minimum quantum cost, minimum number of ancilla inputs and garbage outputs, and the Feynman gate is used to avoid a fanout since a fanout is not allowed in reversible logic. In the existing literature, design methodologies are limited to the design of a ([Formula: see text]) reversible left rotator that can only perform the left rotate operation. This work explores the other primary functionalities of a reversible barrel shifter such as the design of a reversible: (i) logical right shifter, (ii) universal right shifter that supports logical right shifter, arithmetic right shifter and right rotate operation, (iii) bidirectional logical shifter and (iv) universal bidirectional shifter that supports bidirectional logical and arithmetic shifter and rotate operations. The other types of reversible barrel shifters can also be easily designed by making minor modifications in the proposed methodologies. The proposed design methodologies are generic in nature and can be implemented using any barrel shifter of ([Formula: see text]) size, where n and k are the number of data bits and shift value, respectively. In order to minimize the number of ancilla inputs and garbage outputs, strategies such as the implementation of an n number of 2:1 MUXes as a chain of n Fredkin gates and the mapping of the two different 2:1 MUXes that are controlled by a common control signal but having the swapped controlled signals on a single Fredkin gate, are utilized. The design methodologies are evaluated in terms of the number of garbage outputs, the number of ancilla inputs and quantum cost. For a ([Formula: see text]) reversible barrel shifter, the relations between the varying values of n and k and their impact on the number of garbage outputs, the number of ancilla inputs and quantum cost are also established to help the designers in choosing an efficient barrel shifter according to their design needs.

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