scholarly journals Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

2021 ◽  
Vol 23 (09) ◽  
pp. 1313-1325
Author(s):  
Gobinda Karmakar ◽  
◽  
Dr. Saroj Kumar Biswas ◽  
Dr. Ardhendu Mandal ◽  
Arijit Bhattacharya ◽  
...  
Keyword(s):  
Research Area ◽  
Sequential Circuits ◽  
Quantum Cost ◽  
Efficient Design ◽  
Hardware Complexity ◽  
Constant Input ◽  
Reversible Computing ◽  
Main Challenge ◽  
Comparative Review ◽  
Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor

2019 ◽  
Vol 17 (05) ◽  
pp. 1950048
Author(s):  
Abdollah Norouzi Doshanlou ◽  
Majid Haghparast ◽  
Mehdi Hosseinzadeh ◽  
Midia Reshadi
Keyword(s):  
System Performance ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Constant Input ◽  
Comparison Results ◽  
Garbage Output ◽  
First Time

In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.

scholarly journals First Steps in Creating Online Testable Reversible Sequential Circuits

VLSI Design ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-13 ◽  
Author(s):  
Mozammel H. A. Khan ◽  
Jacqueline E. Rice
Keyword(s):  
Research Area ◽  
Sequential Circuits ◽  
Online Testing ◽  
Quantum Cost ◽  
Quantum Dot Cellular Automata ◽  
Replacement Technique ◽  
Feedback Method ◽  
New Research ◽  
Direct Feedback ◽  
Ancilla Inputs

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

scholarly journals A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder

2020 ◽  
Vol 64 (4) ◽  
pp. 343-351
Author(s):  
Sheba Diamond Thabah ◽  
Prabir Saha
Keyword(s):  
Quantum Computer ◽  
Research Area ◽  
Quantum Gates ◽  
Quantum Cost ◽  
Performance Parameters ◽  
Hardware Complexity ◽  
Proper Selection ◽  
Technical Literature ◽  
Gate Count ◽  
Decimal Adder

The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.

scholarly journals A review on reversible logic gates

2020 ◽  
Vol 12 (1) ◽  
pp. 242-250
Author(s):  
B.Y. Galadima ◽  
G.S.M. Galadanci ◽  
A. Tijjani ◽  
M. Ibrahim
Keyword(s):  
Digital Signal ◽  
Logic Gates ◽  
Propagation Delay ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Comparative Review ◽  
Reversible Logic Gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,

scholarly journals Synthesis of sequential circuits by using linearization

2007 ◽  
Vol 20 (3) ◽  
pp. 461-477
Author(s):  
Iliya Levin ◽  
Osnat Keren ◽  
Vladimir Ostrovsky
Keyword(s):  
State Machine ◽  
Sequential Circuits ◽  
Efficient Design ◽  
Linearization Technique ◽  
Logic Functions ◽  
Linearization Techniques

The paper deals with synthesis of sequential circuits defined by their algorithmic state machine notation. Such circuits have a number of specific properties which enable efficient design of the circuits by utilizing so-called linearization techniques. A typical linearization technique includes calculation of autocorrelation values for a system of logic functions corresponding to the circuit. For the mentioned sequential circuits, the calculations which usually require massive computational recourses may be significantly reduced and thus low-overhead implementations of the circuits can be obtained relatively easy. The paper introduces a novel architecture of so-called linearized sequential circuits, and a piece-wise linearization approach for synthesis of sequential circuits. Results are evaluated both analytically and by using a number of standard benchmarks.

General Method to Design Reversible Universal n-Bit Up/Down Counters

2020 ◽  
Vol 29 (10) ◽  
pp. 2050165
Author(s):  
Zeinab Kalantari ◽  
Mohammad Eshghi ◽  
Majid Mohammadi ◽  
Somayeh Jassbi
Keyword(s):  
Power Consumption ◽  
Electronic Devices ◽  
Reducing Power ◽  
Sequential Circuits ◽  
Quantum Cost ◽  
Multiple Outputs ◽  
Reversible Circuits ◽  
Direct Design ◽  
The Common ◽  
General Method

With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [Formula: see text]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([Formula: see text], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.

OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT

2009 ◽  
Vol 18 (02) ◽  
pp. 311-323 ◽  
Author(s):  
MAJID HAGHPARAST ◽  
MAJID MOHAMMADI ◽  
KEIVAN NAVI ◽  
MOHAMMAD ESHGHI
Keyword(s):  
Dna Computing ◽  
Full Adder ◽  
Logic Circuits ◽  
Optical Information ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Cmos Design ◽  
Fair Comparison ◽  
Low Power Cmos ◽  
Significant Attention

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

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