scholarly journals Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs of Regular Three-dimensional Networks, Part II: Formalistic Architecture Realization

2020 ◽  
Vol 11 (6) ◽  
pp. 1-19
Author(s):  
Anas N. Al-Rabadi
Keyword(s):  
Low Power ◽  
Field Emission ◽  
Three Dimensional ◽  
Low Power Design ◽  
Vlsi Circuits ◽  
Lattice Systems ◽  
Controlled Switching ◽  
Compact Size ◽  
Field Emission Devices ◽  
Carbon Based

Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their corresponding carbon-based field emission controlled switching is introduced in this article. The formalistic ternary nano-based implementation utilizes recent findings in field emission and nano applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via field-emission methods. The presented work implements multi-valued Galois functions by utilizing concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first part of the article. The introduced computational extension utilizing many-to-one carbon field-emission devices will be further utilized in implementing congestion-free architectures within the third part of the article. The emerging nano-based technologies form important directions in low-power compact-size regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using much less power than silicon-based devices. Applications include low-power design of VLSI circuits for signal processing and control of autonomous robots.

Parallel processing via carbon field emission-based controlled switching of regular bijective nano systolic networks, part 1: basics

2016 ◽  
Vol 9 (3) ◽  
pp. 274-297
Author(s):  
Anas N. Al-Rabadi
Keyword(s):  
Signal Processing ◽  
Parallel Processing ◽  
Power Consumption ◽  
Low Power ◽  
Field Emission ◽  
Circuit Design ◽  
Minimum Size ◽  
Content Type ◽  
Controlled Switching ◽  
Carbon Based

Purpose The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and the corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding m-ary (many-valued) extensions for the use in nano systolic networks are introduced. The first part of the paper presents important fundamentals with regards to systolic computing and carbon-based field emission that will be utilized in the implementations within the second part of the paper. Design/methodology/approach The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented. Findings Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented. Originality/value The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power very-large-scale-integration circuit design for signal processing applications.

Parallel processing via carbon field emission-based controlled-switching of regular bijective nano systolic networks, Part II

2016 ◽  
Vol 9 (4) ◽  
pp. 369-393
Author(s):  
Anas N. Al-Rabadi
Keyword(s):  
Signal Processing ◽  
Parallel Processing ◽  
Low Power ◽  
Field Emission ◽  
Circuit Design ◽  
Minimum Size ◽  
Content Type ◽  
Design Specifications ◽  
Controlled Switching ◽  
Carbon Based

Purpose The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced. Design/methodology/approach The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented. Findings Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented. Practical implications The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications. Originality/value The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

scholarly journals Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs of Regular Three-dimensional Networks, Part I: Basics

2020 ◽  
Vol 11 (5) ◽  
pp. 1-24
Author(s):  
Anas N. Al-Rabadi
Keyword(s):  
Field Emission ◽  
Carbon Fibers ◽  
Three Dimensional ◽  
Minimum Size ◽  
Dimensional Lattice ◽  
Controlled Switching ◽  
Concurrent Processing ◽  
High Regularity ◽  
Minimum Power Consumption

New implementations within concurrent processing using three-dimensional lattice networks via nano carbon-based field emission controlled-switching is introduced in this article. The introduced nano-based three-dimensional networks utilize recent findings in nano-apex field emission to implement the concurrent functionality of lattice networks. The concurrent implementation of ternary Galois functions using nano threedimensional lattice networks is performed by using carbon field-emission switching devices via nano-apex carbon fibers and nanotubes. The presented work in this part of the article presents important basic background and fundamentals with regards to lattice computing and carbon field-emission that will be utilized within the follow-up works in the second and third parts of the article. The introduced nano-based three-dimensional lattice implementations form new and important directions within three-dimensional design in nanotechnologies that require optimal specifications of high regularity, predictable timing, high testability, fault localization, self-repair, minimum size, and minimum power consumption.

scholarly journals LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES

2020 ◽  
Vol 5 (2) ◽  
pp. 223-232
Author(s):  
Sandeep Singh ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Low Power Design ◽  
Vital Role ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Design Strategies ◽  
Power Devices ◽  
Dynamic Power

In the present day scenario, designing a circuit with low power has become very important and challenging task. The designing of any processor for portable devices demands low power. This can be achieved by incorporating low power design strategies and rules at various stages of design. To increase the performance of portable devices, the power backup should be taken in consideration, which is extremely desirable from the users prospective. As we approaches towards the sub-micron technology the requirement of low power devices increases significantly. But at the same time leakage current and dynamic power dissipation play a vital role to diminish the performance of portable devices. This paper presents techniques to reduce the power dissipation and various methodologies to increase the speed of device. That is very beneficial for designing of future VLSI circuits.

Design of Reversible Shift Register Using Reduced Number of Logic Gates

2020 ◽  
Vol 12 (1) ◽  
pp. 33-37
Author(s):  
Heranmoy Maity ◽  
Sudipta Banerjee ◽  
Arindam Biswas ◽  
Anita Pal ◽  
Anup Kumar Bhattacharjee
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Low Power Design ◽  
Reversible Logic ◽  
Vlsi Circuits ◽  
Shift Register ◽  
Proposed Model ◽  
Low Power Dissipation ◽  
Reversible Logic Gates

Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

scholarly journals Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs of Regular Three-dimensional Networks, Part III: Layout Congestion-free Effectuation

2020 ◽  
Vol 11 (6) ◽  
pp. 21-37
Author(s):  
Anas N. Al-Rabadi
Keyword(s):  
Field Emission ◽  
Autonomous Robots ◽  
Three Dimensional ◽  
Three Dimensions ◽  
Ic Design ◽  
Dimensional Lattice ◽  
Controlled Switching ◽  
Multi Stage ◽  
Special Case ◽  
General Method

Novel layout realizations for congestion-free three-dimensional lattice networks using the corresponding carbon-based field emission controlled switching is introduced in this article. The developed nano-based implementations are performed in three dimensions to perform the required concurrent computations for which two-dimensional implementations are a special case. The introduced realizations for congestion-free concurrent computations utilize the field-emission controlled switching devices that were presented in the first and second parts of the article for the solution of synthesis congestion and by utilizing field-emission from carbon nanotubes and nanotips. Since the concept of symmetry indices has been related to regular logic design, a more general method called Iterative Symmetry Indices Decomposition that produces regular three-dimensional lattice networks via carbon field-emission multiplexing is presented, where one obtains multi-stage decompositions whenever volume-specific layout constraints have to be satisfied. The introduced congestion-free nano-based lattice computations form new and important paths in regular lattice realizations, where applications include low-power IC design for the control of autonomous robots and for signal processing implementations.

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