Impact Toughness Modification of NIST Low-Energy Charpy Verification Specimens for Testing at Room Temperature

The possibility for the National Institute for Standards and Technology (NIST) to certify Charpy reference specimens for testing at room temperature (21 °C ± 1 °C) instead of −40 °C was investigated in a previous study, in which a slightly increased likelihood of specimen jamming was observed at the low-energy level (13 J to 20 J). Moreover, there is a concern that the higher impact toughness of low-energy verification specimens at room temperature would not allow the same Charpy machine features to be verified as in the case of low-temperature (−40 °C) tests, namely, the linear elastic behavior of the sample and the very high maximum forces (typically larger than 33 kN). In this paper, we report on the change in the mechanical properties (hardness and absorbed energy) of the American Iron and Steel Institute (AISI) 4340 steel low-energy specimens that ensues from the modification of the temperature of the final tempering heat treatment. We established that, if low-energy verification specimens are tempered at 300 °C for 2 h and then air cooled, they exhibit equivalent impact toughness (13 J to 20 J) and postimpact behavior (specimen halves projected backward at high speed) at room temperature as compared to specimens currently on sale for testing at −40 °C. Their hardness is however increased to above 49 HRC on the Rockwell scale. The minimum hardness requirement for low-energy verification specimens, currently set at 44 HRC in NIST specifications, will have to be increased to 49 HRC.

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Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499323 ◽

2002 ◽

Cited By ~ 7

Author(s):

M. Ugajin ◽

J. Kodate ◽

Y. Kobayashi ◽

S. Konaka ◽

T. Sakai

Keyword(s):

High Speed ◽

High Performance ◽

Bipolar Transistors ◽

Low Energy ◽

Process Technology ◽

Ultra High Speed ◽

Very High

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Dislocation structures around SiO2 Particles in aged Cu-Cr-SiO2

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100110118 ◽

1978 ◽

Vol 36 (1) ◽

pp. 594-595

Author(s):

N.J. Long ◽

M.H. Loretto ◽

C.H. Lloyd

Keyword(s):

Flow Stress ◽

Single Crystals ◽

Room Temperature ◽

Thin Foil ◽

Age Hardening ◽

Dispersion Strengthening ◽

Accurate Picture ◽

The Matrix ◽

Very High ◽

Good Agreement

IntroductionThere have been several t.e.m. studies (1,2,3,4) of the dislocation arrangements in the matrix and around the particles in dispersion strengthened single crystals deformed in single slip. Good agreement has been obtained in general between the observed structures and the various theories for the flow stress and work hardening of this class of alloy. There has been though some difficulty in obtaining an accurate picture of these arrangements in the case when the obstacles are large (of the order of several 1000's Å). This is due to both the physical loss of dislocations from the thin foil in its preparation and to rearrangement of the structure on unloading and standing at room temperature under the influence of the very high localised stresses in the vicinity of the particles (2,3).This contribution presents part of a study of the Cu-Cr-SiO2 system where age hardening from the Cu-Cr and dispersion strengthening from Cu-Sio2 is combined.

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Structural changes in silicon-on-insulator material during post-implantation annealing

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100145054 ◽

1986 ◽

Vol 44 ◽

pp. 736-737

Author(s):

C. O. Jung ◽

S. J. Krause ◽

S.R. Wilson

Keyword(s):

Integrated Circuits ◽

Oxide Layer ◽

High Speed ◽

Structural Changes ◽

Device Fabrication ◽

Silicon On Insulator ◽

High Quality ◽

Radiation Hardened ◽

Post Implantation ◽

Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

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TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100138713 ◽

1995 ◽

Vol 53 ◽

pp. 468-469

Author(s):

N. David Theodore ◽

Donald Y.C Lie ◽

J. H. Song ◽

Peter Crozier

Keyword(s):

Integrated Circuits ◽

Heterojunction Bipolar Transistors ◽

Integrated Circuit ◽

High Speed ◽

Room Temperature ◽

Strain Relaxation ◽

Bipolar Transistors ◽

Sige Hbt ◽

Integrated Circuit Manufacturing ◽

Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

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Very High Speed Integrated Circuits/Gallium Arsenide Electronics for Aircraft Engine Controls

10.23919/acc.1988.4790024 ◽

1988 ◽

Author(s):

Mark A. Overstreet

Keyword(s):

Gallium Arsenide ◽

Integrated Circuits ◽

High Speed ◽

Aircraft Engine ◽

Very High

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YSS HAP72

Alloy Digest ◽

10.31399/asm.ad.ts0779 ◽

2019 ◽

Vol 68 (10) ◽

Keyword(s):

Wear Resistance ◽

High Temperature ◽

Powder Metallurgy ◽

Tool Steel ◽

High Speed ◽

High Wear Resistance ◽

Bend Strength ◽

Temperature Performance ◽

Very High

Abstract YSS HAP72 is a powder metallurgy high-speed tool steel with a very high wear resistance. This datasheet provides information on composition, hardness, and bend strength. It also includes information on high temperature performance. Filing Code: TS-779. Producer or source: Hitachi Metals America Ltd.

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