Data Compression And Recovery For Power Consumption At Specific Time Instances And In Peak Periods

2013 ◽  
Author(s):  
Tetiana Lutchyn ◽  
Bernt Lie ◽  
Anatoliy Voloshko
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Specific Time

scholarly journals The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

2021 ◽  
Vol 9 (1) ◽  
pp. 456-460
Author(s):  
Syamala Yarlagadda, Srilakshmi Kaza, Anil chowdary Tummala, E Vijaya Babu, R. Prabhakar
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Huge Amount ◽  
Significant Time ◽  
Planar Structures ◽  
Fpga Architecture ◽  
Bus Encoding ◽  
Bus Structure ◽  
Using Data ◽  
Encoding Method

In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.

scholarly journals Multi-Channel Neural Recording Implants: A Review

Sensors ◽  
2020 ◽  
Vol 20 (3) ◽  
pp. 904 ◽  
Author(s):  
Fereidoon Hashemi Noshahr ◽  
Morteza Nabavi ◽  
Mohamad Sawan
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Data Converters ◽  
Neural Recording ◽  
The Body ◽  
System Architectures ◽  
Silicon Area ◽  
Analog To Digital ◽  
Reduction Techniques ◽  
Signal Features

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain–machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

scholarly journals C-Pack: Cache Compression for Microprocessor Performance

2011 ◽  
pp. 102-107
Author(s):  
T. Narasimhulu
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Lossless Compression ◽  
Register Transfer Level ◽  
Improve Performance ◽  
Memory Hierarchies ◽  
Compression Algorithms ◽  
Cache Line ◽  
On Line ◽  
Cache Compression

Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, most past work, and all work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. In this work, I present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. The algorithm has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. We reduced the proposed algorithm to a register transfer level hardware design, permitting performance, power consumption, and area estimation.

Exploiting DLMS/COSEM Data Compression To Learn Power Consumption Patterns

2021 ◽  
Author(s):  
Marcell Feher ◽  
Daniel E. Lucani ◽  
Morten Tranberg Hansen ◽  
Flemming Enevold Vester
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Consumption Patterns

A real time ECG data compression scheme for enhanced bluetooth low energy ECG system power consumption

2017 ◽  
Author(s):  
Ahmed Faeq Hussein ◽  
Shaiful Jahari Hashim ◽  
Ahmad Fazli Abdul Aziz ◽  
Fakhrul Zaman Rokhani ◽  
Wan Azizun Wan Adnan
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Real Time ◽  
Low Energy ◽  
Compression Scheme ◽  
Bluetooth Low Energy ◽  
Ecg Data Compression ◽  
System Power ◽  
Ecg Data

scholarly journals A Wireless Electro-Optic Platform for Multimodal Electrophysiology and Optogenetics in Freely Moving Rodents

2021 ◽  
Vol 15 ◽  
Author(s):  
Guillaume Bilodeau ◽  
Gabriel Gagnon-Turcotte ◽  
Léonard L. Gagnon ◽  
Iason Keramidis ◽  
Igor Timofeev ◽  
...  
Keyword(s):  
Signal Processing ◽  
Motor Cortex ◽  
Power Consumption ◽  
Data Compression ◽  
Local Field ◽  
Data Reduction ◽  
Action Potentials ◽  
Field Potentials ◽  
Electro Optic ◽  
Freely Moving

This paper presents the design and the utilization of a wireless electro-optic platform to perform simultaneous multimodal electrophysiological recordings and optogenetic stimulation in freely moving rodents. The developed system can capture neural action potentials (AP), local field potentials (LFP) and electromyography (EMG) signals with up to 32 channels in parallel while providing four optical stimulation channels. The platform is using commercial off-the-shelf components (COTS) and a low-power digital field-programmable gate array (FPGA), to perform digital signal processing to digitally separate in real time the AP, LFP and EMG while performing signal detection and compression for mitigating wireless bandwidth and power consumption limitations. The different signal modalities collected on the 32 channels are time-multiplexed into a single data stream to decrease power consumption and optimize resource utilization. The data reduction strategy is based on signal processing and real-time data compression. Digital filtering, signal detection, and wavelet data compression are used inside the platform to separate the different electrophysiological signal modalities, namely the local field potentials (1–500 Hz), EMG (30–500 Hz), and the action potentials (300–5,000 Hz) and perform data reduction before transmitting the data. The platform achieves a measured data reduction ratio of 7.77 (for a firing rate of 50 AP/second) and weights 4.7 g with a 100-mAh battery, an on/off switch and a protective plastic enclosure. To validate the performance of the platform, we measured distinct electrophysiology signals and performed optogenetics stimulation in vivo in freely moving rondents. We recorded AP and LFP signals with the platform using a 16-microelectrode array implanted in the primary motor cortex of a Long Evans rat, both in anesthetized and freely moving conditions. EMG responses to optogenetic Channelrhodopsin-2 induced activation of motor cortex via optical fiber were also recorded in freely moving rodents.

Optimization of Power Allocation in Multimedia Wireless Sensor Networks

2013 ◽  
Vol 1 (1) ◽  
pp. 56-68 ◽  
Author(s):  
Ming Yang ◽  
Dajin Wang ◽  
Nikolaos Bourbakis
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Power Consumption ◽  
Data Compression ◽  
Video Compression ◽  
Data Transmission ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Wireless Multimedia ◽  
Monitoring And Surveillance

Wireless Sensor Networks (WSN) have been widely applied in monitoring and surveillance fields in recent years and have dramatically changed the methodologies and technologies in monitoring and surveillance. However, the sensor nodes in WSN have very limited computing resources and power supply, and thus the maximization of network life is a very critical issue. In the newly-emerging Wireless Multimedia Sensor Network (WMSN), the high volume of sensed video data needs to be compressed before transmission. Different video coding schemes have been developed and applied to wireless multimedia sensor networks, and there exists a tradeoff between the power consumption of data compression and that of data transmission. Video compression will reduce the amount of data that needs to be transmitted and thus the amount of power consumed for data transmission; however, too much video compression will consume excessive power which outweighs the power savings on data transmission. Thus, how to reach an optimized balance between compression and transmission and maximize network life becomes a challenging research issue. In this paper, the authors propose mathematical models which describe power consumptions of data compression and transmission of sensor nodes in hexagon-shaped clusters. Under the proposed model, they have achieved the optimized data compression ratio which can minimize the overall power consumption of the whole cluster.

Compositional Tuning of Negative Differential Resistance in Bulk Silver Iodide Memristor

2020 ◽  
Author(s):  
SMITA GAJANAN NAIK ◽  
Mohammad Hussain Kasim Rabinal
Keyword(s):  
Power Consumption ◽  
Negative Differential Resistance ◽  
Silver Iodide ◽  
Differential Resistance ◽  
Fast Response ◽  
Low Power Consumption ◽  
Switching Effect ◽  
Memory Switching ◽  
Bulk Silver ◽  
Emerging Memory

Electrical memory switching effect has received a great interest to develop emerging memory technology such as memristors. The high density, fast response, multi-bit storage and low power consumption are their...

Sign in / Sign up

Export Citation Format

Share Document