scholarly journals Multi-Channel Neural Recording Implants: A Review

Sensors ◽  
2020 ◽  
Vol 20 (3) ◽  
pp. 904 ◽  
Author(s):  
Fereidoon Hashemi Noshahr ◽  
Morteza Nabavi ◽  
Mohamad Sawan
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Data Converters ◽  
Neural Recording ◽  
The Body ◽  
System Architectures ◽  
Silicon Area ◽  
Analog To Digital ◽  
Reduction Techniques ◽  
Signal Features

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain–machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

2021 ◽  
Author(s):  
Daniel Junehee Lee
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Sar Adc ◽  
Least Significant Bit ◽  
Silicon Area ◽  
Analog To Digital ◽  
Power Efficient ◽  
Successive Approximation Register ◽  
Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

scholarly journals A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1078
Author(s):  
Thi Thuy Pham ◽  
Dongmin Kim ◽  
Seo-Hyeong Jeong ◽  
Junghyup Lee ◽  
Donggu Im
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Supply Voltage ◽  
Current Source ◽  
Low Noise ◽  
The Body ◽  
Common Source ◽  
Conversion Gain ◽  
Input Transistor ◽  
Envelope Detector

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

scholarly journals Direct measurement of vagal tone in rats does not show correlation to HRV

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Joseph T. Marmerstein ◽  
Grant A. McCallum ◽  
Dominique M. Durand
Keyword(s):  
Heart Failure ◽  
Heart Rate ◽  
Heart Rate Variability ◽  
Neural Activity ◽  
Vagal Tone ◽  
Neural Recording ◽  
The Body ◽  
Autonomic Nerve ◽  
Vagal Activity ◽  
Recording Technology

AbstractThe vagus nerve is the largest autonomic nerve, innervating nearly every organ in the body. “Vagal tone” is a clinical measure believed to indicate overall levels of vagal activity, but is measured indirectly through the heart rate variability (HRV). Abnormal HRV has been associated with many severe conditions such as diabetes, heart failure, and hypertension. However, vagal tone has never been directly measured, leading to disagreements in its interpretation and influencing the effectiveness of vagal therapies. Using custom carbon nanotube yarn electrodes, we were able to chronically record neural activity from the left cervical vagus in both anesthetized and non-anesthetized rats. Here we show that tonic vagal activity does not correlate with common HRV metrics with or without anesthesia. Although we found that average vagal activity is increased during inspiration compared to expiration, this respiratory-linked signal was not correlated with HRV either. These results represent a clear advance in neural recording technology but also point to the need for a re-interpretation of the link between HRV and “vagal tone”.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

scholarly journals The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

2021 ◽  
Vol 9 (1) ◽  
pp. 456-460
Author(s):  
Syamala Yarlagadda, Srilakshmi Kaza, Anil chowdary Tummala, E Vijaya Babu, R. Prabhakar
Keyword(s):  
Power Consumption ◽  
Data Compression ◽  
Huge Amount ◽  
Significant Time ◽  
Planar Structures ◽  
Fpga Architecture ◽  
Bus Encoding ◽  
Bus Structure ◽  
Using Data ◽  
Encoding Method

In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.

scholarly journals A Smart Binaural Hearing Aid Architecture Based on a Mobile Computing Platform

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 811
Author(s):  
Yingdan Li ◽  
Fei Chen ◽  
Zhuoyi Sun ◽  
Zhaoyang Weng ◽  
Xian Tang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Mobile Computing ◽  
User Experience ◽  
Speech Enhancement ◽  
Hearing Aids ◽  
Hearing Aid ◽  
Binaural Hearing ◽  
The Body ◽  
Processing Unit ◽  
Computing Platform

This paper presents a new structure for hearing aids. Normally, the power consumption and user experience are contradictory. The proposed hearing aid structure mainly consists of three parts: the earpieces, the mobile computing platform, and the real-time speech-enhancement application. It can run complex algorithms without carrying out heavy calculations on the processors in the hearing aid. Thus, the binaural algorithm is utilized without being limited by complexity and power consumption to improve the user experience. Moreover, the speech-enhancement algorithm can be updated much more easily than in traditional built-in digital signal process hearing aids. A good level of user experience is achieved by combining the hearing aid and mobile computing platform with a 400-MHz transceiver; furthermore, the 400-MHz transceiver can reduce path loss around the body. The concept verification process showed that the overall usage of the central processing unit in the smartphone is around 16%, the signal-to-noise ratios show at least a 30% improvement in some environments, and the whole system delay is 8.8 ms. The presented objective and subjective results show significant improvements regarding user experience and usability brought about by the proposed structure.

Analysis and comparison of fast multiplier circuits based on different parameters

2018 ◽  
Vol 7 (3) ◽  
pp. 1189
Author(s):  
Mr Aaron D’costa ◽  
Dr Abdul Razak ◽  
Dr Shazia Hasan
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Electronic Circuit ◽  
Vlsi Circuit ◽  
Silicon Area ◽  
Lower Power ◽  
Digital Electronics ◽  
Design Specifications ◽  
Important Design ◽  
Multiplier Circuit

Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.  

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