scholarly journals Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 441
Author(s):  
Marcello Cioni ◽  
Alessandro Bertacchini ◽  
Alessandro Mucci ◽  
Nicolò Zagni ◽  
Giovanni Verzellesi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Driving Voltage ◽  
Drain Voltage ◽  
Current Increase ◽  
Mode Operation ◽  
Switch Mode ◽  
Gate Signal ◽  
A Current ◽  
Parameter Monitoring

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

scholarly journals Effects of Doping Concentration on Device Performance of GaN-based Nano-regime MOSFETs

2017 ◽  
Vol 16 (1) ◽  
pp. 69-74
Author(s):  
Md Iktiham Bin Taher ◽  
Md. Tanvir Hasan
Keyword(s):  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Gate Length ◽  
Drain Voltage ◽  
Switching Device ◽  
Device Applications

Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are promising for switching device applications. The doping of n- and p-layers is varied to evaluate the figure of merits of proposed devices with a gate length of 10 nm. Devices are switched from OFF-state (gate voltage, VGS = 0 V) to ON-state (VGS = 1 V) for a fixed drain voltage, VDS = 0.75 V. The device with channel doping of 1×1016 cm-3 and source/drain (S/D) of 1×1020 cm-3 shows good device performance due to better control of gate over channel. The ON-current (ION), OFF-current (IOFF), subthreshold swing (SS), drain induce barrier lowering (DIBL), and delay time are found to be 6.85 mA/μm, 5.15×10-7 A/μm, 87.8 mV/decade, and 100.5 mV/V, 0.035 ps, respectively. These results indicate that GaN-based MOSFETs are very suitable for the logic switching application in nanoscale regime.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2011 ◽  
Vol 679-680 ◽  
pp. 607-612 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Kazuto Takao ◽  
Masaru Furukawa ◽  
Makoto Mizukami ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitor ◽  
Time Dependent Dielectric Breakdown ◽  
Blocking Voltage ◽  
Switching Characteristics

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

Metal-oxide Semiconductor Field-effect Transistors using Single ZnO Nanowire

2004 ◽  
Vol 829 ◽  
Author(s):  
Young-Woo Heo ◽  
B. S. Kang ◽  
L. C. Tien ◽  
Y. Kwon ◽  
J. R. La Roche ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Ultra Violet ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Zno Nanowire ◽  
Current Increase ◽  
Uv Illumination ◽  
Source Current

ABSTRACTSingle ZnO nanowire metal-oxide semiconductor field effect transistors (MOSFETs) were fabricated using nanowires grown by site selective Molecular Beam Epitaxy. When measured in the dark at 25°C, the depletion-mode transistors exhibit good saturation behavior, a threshold voltage of ∼-3V and a maximum transconductance of order 0.3 mS/mm. Under ultra-violet (366nm) illumination, the drain-source current increase by approximately a factor of 5 and the maximum transconductance is ∼ 5 mS/mm. The channel mobility is estimated to be ∼3 cm2 /V.s, which is comparable to that reported for thin film ZnO enhancement mode MOSFETs and the on/off ratio was ∼25 in the dark and ∼125 under UV illumination.

scholarly journals Extraction of Junction Temperature of SiC MOSFET Module Based on Turn-On dIDS/dt

Energies ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 1951 ◽  
Author(s):  
Delei Huang ◽  
Guojun Tan ◽  
Chengfei Geng ◽  
Jingwei Zhang ◽  
Chang Liu
Keyword(s):  
Printed Circuit Board ◽  
Field Effect Transistors ◽  
Rogowski Coil ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Junction Temperature ◽  
Driving Voltage ◽  
Factors Affecting ◽  
Turn On ◽  
Gate Resistance

In this paper, a method of extracting the junction temperature based on the turn-on current switching rate (dIDS/dt) of silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) is proposed. The temperature dependence of dIDS/dt is analyzed theoretically, and experimentally to show that dIDS/dt increases with the rising junction temperature. In addition, other factors affecting dIDS/dt are also discussed by using the fundamental device physics equations and experiments. The result shows that the increase of the DC-link voltage VDC, the external gate resistance RG-ext, and the decrease of the driving voltage VGG can increase the temperature sensitivity of the dIDS/dt. A PCB (printed circuit board) Rogowski coil measuring circuit based on the fact that the SiC MOSFET chip temperature and dIDS/dt is estimated in a linear way is designed to obtain the junction temperature. The experimental results demonstrate that the proposed junction temperature extracting is effective.

scholarly journals Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain

Coatings ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 654
Author(s):  
Eunjung Ko ◽  
Juhee Lee ◽  
Seung Wook Ryu ◽  
Hyunsu Shin ◽  
Seran Park ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Saturation Current ◽  
Drain Voltage ◽  
Drain Region ◽  
P Type ◽  
Beam Diffraction ◽  
Significant Attention

Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized.

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors

2005 ◽  
Vol 87 (9) ◽  
pp. 092104 ◽  
Author(s):  
S. Hosokawa ◽  
D. Navarro ◽  
M. Miura-Mattausch ◽  
H. J. Mattausch ◽  
T. Ohguro ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Voltage Dependence ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Length ◽  
Drain Voltage

scholarly journals Performance Study of Pentacene based Organic Field Effect Transistor by Using monolayer, bilayer and trilayer and Gate Insulators

2020 ◽  
Vol 18 (44) ◽  
pp. 85-97
Author(s):  
Bushra H. Mohammed ◽  
Estabraq Talib Abdullah
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Performance ◽  
Output Curve ◽  
Drain Voltage ◽  
Performance Study ◽  
Current Increase ◽  
Gate Insulators ◽  
Effect Transistor

In this paper, Pentacene based-organic field effect transistors (OFETs) by using monolayer , bilayer and three layers of three  different gate insulators (ZrO2, PVA and CYEPL) , two layers of different gate insulators (ZrO2/PVA and ZrO2/CYEPL  ) and three layers of different gate insulators (ZrO2/PVA/CYEPL) were studied its electrical performance (output (Id-Vd)and transfer(Id-Vg) characteristics)by using the gradual-channel approximation model. The device exhibits a typical output curve of a field-effect transistor (FET). Furthermore, analysis of electrical characterization was done to investigate the source-drain voltage (Vd) dependent current and note The effects of gate dielectric on electrical performance for OFET. As this work  take account of  effect capacitance semiconductor in performance OFETs. The values of current which calculated using MATLAB simulation exhibited a value of current increase with increasing source-drain voltage.  Also the Organic Transistor modeling software was used to evaluate the transconductance calculated.

14.6 mΩcm2 3.3 kV DIMOSFET on 4H-SiC (000-1)

2014 ◽  
Vol 778-780 ◽  
pp. 935-938 ◽  
Author(s):  
Hiroshi Kono ◽  
Masaru Furukawa ◽  
Keiko Ariyoshi ◽  
Takuma Suzuki ◽  
Yasunori Tanaka ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Current Spread ◽  
Blocking Voltage

Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.

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