scholarly journals Multichannel ADC IP Core on Xilinx SoC FPGA

2021 ◽  
Author(s):  
A. Suresh ◽  
S. Shyama ◽  
Sangeeta Srivastava ◽  
Nihar Ranjan
Keyword(s):  
Data Transfer ◽  
Ip Core ◽  
Serial Interface ◽  
Analog Signals ◽  
Layout Area ◽  
Integrated Logic ◽  
Small Form Factor ◽  
Source Sink ◽  
Time Division ◽  
Parallel Interface

Sensing of analogue signals such as voltage, temperature, pressure, current etc. is required to acquire the real time analog signals in the form digital streams. Most of the static analog signals are converted into voltage using sensors, transducers etc. and then measured using ADCs. The digitized samples from ADC are collected either through serial or parallel interface and processed by the programmable chips such as processors, controllers, FPGAs, SOCs etc. In some cases, Multichannel supported ADCs are used to save the layout area when the functionalities are to be realized in a small form factor. In such scenarios, parallel interface for each channel is not a preferred interface considering the more number of interfaces / traces between the components. Hence, Custom, Sink synchronized, Configurable multichannel ADC soft IP core has been developed using VHDL coding to interwork with multichannel supported, time division multiplexed ADCs with serial interface. The developed IP core can be used either as it is with the SPI interface as specified in this paper or with necessary modifications / configurations. The configurations can be the number of channels, sample size, sampling frequency, data transfer clock, type of synchronization – source / sink, control signals and the sequence of the operations performed to configure ADC. The efficiency of implementation is validated using the measurements of throughput, and accuracy for the required range of input with acceptable tolerances. ZYNQ FPGA and LTC2358 ADC are used to evaluate the developed IP core. Integrated Logic Analyser (ILA) which is an integrated verification tool of Vivado is used for Verification.

Design of Equivalent Device Based on Ethernet Communication

2011 ◽  
Vol 341-342 ◽  
pp. 868-872
Author(s):  
Hui Xin Zhang ◽  
Yan Lu Zheng ◽  
Yan Ran Chen ◽  
Hai Guang Yang
Keyword(s):  
Measurement System ◽  
High Speed ◽  
Data Transfer ◽  
Long Distance ◽  
Aircraft Measurement ◽  
Transfer Mode ◽  
Analog Signals ◽  
Self Testing ◽  
Test Platform ◽  
Equivalent Test

To match, test, and determine the working conditions and correctness of each function of the aircraft measurement system. This article proposes a design of equivalent test platform which can produce digital and analog signals for the self-testing of measurement system. By using the ethernet protocol chip W5300 to achieve the high-speed communication between host computer and equivalent device. Communication uses UDP unicast data transfer mode with advantages of high-speed and long-distance transmission, and the Phenomenon of data packet loss is not easy in transmission.

Design and Verification for Data Interface 8051_USB IP Core

2013 ◽  
Vol 321-324 ◽  
pp. 387-390
Author(s):  
Ya Li Chen ◽  
Li Kun Zheng ◽  
Zhe Ying Li
Keyword(s):  
Data Acquisition ◽  
Data Transfer ◽  
Mass Storage ◽  
Ip Core ◽  
Verilog Hdl ◽  
Storage Devices ◽  
Usb Interface ◽  
Efficient Data

A series of portable mass storage devices are arising due to the effective support from USB interface for its special features, such as easy to use, a high transfer speed and low price. 8051_USB IP core is to achieve data acquisition and efficient data transfer to PC. The abstract of USB Protocol is introduced firstly. Then the design and verification of 8051_USB IP core are discussed in detail. Modules of 8051_USB protocol controller are designed with Verilog HDL. The design is simulated with Modelsim.

scholarly journals Design of domestic serial and parallel interface module

2021 ◽  
Vol 248 ◽  
pp. 03032
Author(s):  
Guowei Shao ◽  
Quanyu Sun ◽  
Sun Yi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Hardware Design ◽  
Serial Port ◽  
Ip Core ◽  
Time System ◽  
Interface Module ◽  
Internal Integration ◽  
Parallel Interface

Domestic serial and parallel interface module is based on domestic high performance FPGA CPCIE module. This type of FPGA has rich logical resources and internal integration of a variety of high-speed interfaces, such as PCIE, high-speed Serdes interface, which can achieve serial port, time system, network and other interfaces design, greatly simplifying the hardware design of the module. The main communication interfaces, PCIE and UART, are realized by the IP core of FPGA, realizing the integration of the main functions on the chip, which greatly improves the flexibility and expansibility of the design.

Characterization of Fine-Pitch Interconnections (≤ 10 μm) on Silicon Interconnect Fabric for Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000556-000560 ◽  
Author(s):  
SivaChandra Jangam ◽  
Adeel Bajwa ◽  
Kannan K. Thankappan ◽  
Subramanian S. Iyer
Keyword(s):  
Data Transfer ◽  
Heterogeneous Integration ◽  
Thermal Compression ◽  
Integration Platform ◽  
Fine Pitch ◽  
Data Rates ◽  
Metal Metal ◽  
Conventional Systems ◽  
Parallel Interface

Abstract We propose a fine-pitch, highly scalable, heterogeneous integration platform called the Silicon-Interconnect Fabric (Si-IF) where dielets are assembled with fine-pitch interconnects (≤ 10 μm) at short inter-dielet spacings (≤ 100 μm) using direct metal-metal Thermal Compression Bonding process (TCB). As a result, short links on Si-IF (≤ 500 μm) are used for inter-dielet communication, reducing the latency to ≤ 35 ps. We experimentally demonstrated the measured insertion loss in these short Si-IF links (≤ 500 μm) is ≤ 2 dB for frequencies up to 30 GHz. Consequently, we show that assemblies on Si-IF have 10–40X lower parasitic inductance, and 7–35X lower parasitic capacitance compared to assemblies on interposers and PCBs. We propose the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol for data transfer that efficiently utilizes the Si-IF to achieve data-rates of ≥ 10 Gbps/link at an energy/bit of ≤ 0.04 pJ/b. Further, the aggregate bandwidth/mm is ≥ 8 Tbps/mm. This corresponds to an improvement of 120–300X in bandwidth/mm and a reduction of 100–500X in energy/bit compared to conventional systems.

scholarly journals Throughput optimization of multi-hop and multi-path cooperation in WPSNs with hardware noises

2021 ◽  
Vol 17 (6) ◽  
pp. 155014772110248
Author(s):  
Lina Yuan ◽  
Huajun Chen ◽  
Jing Gong
Keyword(s):  
Time Allocation ◽  
Sensor Nodes ◽  
Source Node ◽  
Sink Node ◽  
Throughput Optimization ◽  
Simulation Experiments ◽  
Second Stage ◽  
Source Sink ◽  
Time Division ◽  
Achievable Data Rate

This paper proposes a novel multi-path and multi-hop wireless powered sensor network in case of hardware impairment, constituting an energy node, one source node, single sink node, and a series of distributed relay sensor nodes, where the energy node transmits wireless energy to all terminals in the first stage, and the relay sensor nodes relay the information of the source node to the sink node in the second stage. There exists M available paths between the source node and sink node, one of which is chosen for serving source-sink communication. To enhance the minimum achievable data rate, we propose a multi-hop communication protocol based on time-division-multiple-access and an optimal throughput path algorithm. We formulate the time allocation optimization problem about energy and information transmission of the proposed multi-hop cooperation, and confirm through abundant simulation experiments that the proposed scheme can availably improve user unfairness and spectral efficiency, and thus enhance its throughput performance.

SPECTRA: A program for processing electron images of crystals

1992 ◽  
Vol 50 (1) ◽  
pp. 132-133
Author(s):  
M.F. Schmid ◽  
R. Dargahi ◽  
M. W. Tam
Keyword(s):  
Lattice Distortion ◽  
Data Transfer ◽  
Reciprocal Lattice ◽  
Data Entry ◽  
Image Data ◽  
Distortion Correction ◽  
Specimen Preparation ◽  
Electron Image ◽  
Computer Controlled ◽  
Program Modules

Electron crystallography is an emerging field for structure determination as evidenced by a number of membrane proteins that have been solved to near-atomic resolution. Advances in specimen preparation and in data acquisition with a 400kV microscope by computer controlled spot scanning mean that our ability to record electron image data will outstrip our capacity to analyze it. The computed fourier transform of these images must be processed in order to provide a direct measurement of amplitudes and phases needed for 3-D reconstruction.In anticipation of this processing bottleneck, we have written a program that incorporates a menu-and mouse-driven procedure for auto-indexing and refining the reciprocal lattice parameters in the computed transform from an image of a crystal. It is linked to subsequent steps of image processing by a system of data bases and spawned child processes; data transfer between different program modules no longer requires manual data entry. The progress of the reciprocal lattice refinement is monitored visually and quantitatively. If desired, the processing is carried through the lattice distortion correction (unbending) steps automatically.

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